Jitter applying circuit and test apparatus
There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an oscillating signal corresponding to a given reference signal, a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed, a low-frequency application section for applying low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data and a high-frequency application section for applying high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data.
1. A jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, comprising:
a PLL circuit for generating an oscillating signal corresponding to a given reference signal;
a variable delay circuit for outputting said clock signal of said delayed oscillating signal;
a low-frequency application section for applying a low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data; and
a high-frequency application section for applying a high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data,
wherein said PLL circuit has a voltage controlled oscillator for generating said oscillating signal having frequency corresponding to given control voltage;
a phase comparator for generating said control voltage based on a result of comparison of the phase of the given reference signal and the phase of said oscillating signal; and
a low-pass filter for removing the high-frequency component of said control voltage to give to said voltage controlled oscillator, and said low-frequency application section superimposes voltage corresponding to said jitter data to said control voltage generated by said phase comparator and inputs it to said low-pass filter, and
wherein an oscillating signal generated by a voltage controlled oscillator is fed back to the phase comparator via a frequency divider, said feed back is performed inside of a PLL circuit.
2. The jitter application circuit as set forth in claim 1 , wherein said high-frequency application section has a high-pass filter for sampling the high-frequency component of said jitter data.
3. The jitter application circuit as set forth in claim 2 , wherein said low-frequency application section has a low-pass filter for sampling the low-frequency component of said jitter data.
4. The jitter application circuit as set forth in claim 1 , wherein said jitter data is digital data of a plurality of bits;
said high-frequency application section controls a delay in said variable delay circuit based on a low-order bit of a predetermined digit of said jitter data; and
said low-frequency application section controls oscillation frequency of said PLL circuit based on upper-order bit of a predetermined digit of said jitter data.
5. A jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, comprising:
a PLL circuit for generating an oscillating signal corresponding to a given reference signal;
a variable delay circuit for outputting said clock signal of said delayed oscillating signal;
a low-frequency application section for applying a low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data; and
a high-frequency application section for applying a high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data,
wherein said PLL circuit has a voltage controlled oscillator for generating said oscillating signal having frequency corresponding to given control voltage;
a phase comparator for generating said control voltage based on a result of comparison of phase of a given reference signal and phase of said clock signal outputted from said variable delay circuit;
and a low-pass filter for removing the high-frequency component of said control voltage to give to said voltage controlled oscillator, and
wherein a clock signal outputted by the variable delay circuit is fed back to the phase comparator via a frequency divider, said feed back is performed inside of a PLL circuit.
6. The jitter application circuit as set forth in claim 5 , wherein said high-frequency application section has a high-pass filter for sampling the high-frequency component of said jitter data.
7. The jitter application circuit as set forth in claim 6 , wherein said low-frequency application section has a low-pass filter for sampling the low-frequency component of said jitter data.
8. The jitter application circuit as set forth in claim 5 , wherein said jitter data is digital data of a plurality of bits;
said high-frequency application section controls a delay in said variable delay circuit based on a low-order bit of a predetermined digit of said jitter data; and
said low-frequency application section controls oscillation frequency of said PLL circuit based on upper-order bit of a predetermined digit of said jitter data.
9. A test apparatus for testing jitter resistance of an electronic device, comprising:
a pattern generator for generating a test pattern for testing said electronic device;
a timing generator for generating a clock signal containing a phase jitter component corresponding to given jitter data; and
a waveform forming device for inputting the test signal based on said test pattern to said electronic device with timing corresponding to said clock signal:
said timing generator has a PLL circuit for generating an oscillating signal corresponding to a given reference signal;
a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed; a low-frequency application circuit for controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data to apply the low-frequency component of said phase jitter component to said oscillating signal; and a high-frequency application section for controlling a delay in said variable delay circuit based the high-frequency component of said jitter data to apply the high-frequency component of said phase jitter component to said clock signal,
wherein said PLL circuit has a voltage controlled oscillator for generating said oscillating signal having frequency corresponding to given control voltage;
a phase comparator for generating said control voltage based on a result of comparison of the phase of the given reference signal and the phase of said oscillating signal;
and a low-pass filter for removing the high-frequency component of said control voltage to give to said voltage controlled oscillator, and said low-frequency application section superimposes voltage corresponding to said jitter data to said control voltage generated by said phase comparator and inputs it to said low-pass filter, and
wherein an oscillating signal generated by a voltage controlled oscillator is fed back to the phase comparator via a frequency divider, said feed back is performed inside of a PLL circuit.
10. A test apparatus for testing jitter resistance of an electronic device, comprising:
a pattern generator for generating a test pattern for testing said electronic device;
a timing generator for generating a clock signal containing a phase jitter component corresponding to given jitter data; and
a waveform forming device for inputting the test signal based on said test pattern to said electronic device with timing corresponding to said clock signal:
said timing generator has a PLL circuit for generating an oscillating signal corresponding to a given reference signal;
a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed;
a low-frequency application circuit for controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data to apply the low-frequency component of said phase jitter component to said oscillating signal; and
a high-frequency application section for controlling a delay in said variable delay circuit based the high-frequency component of said jitter data to apply the high-frequency component of said phase jitter component to said clock signal,
wherein said PLL circuit has a voltage controlled oscillator for generating said oscillating signal having frequency corresponding to given control voltage;
a phase comparator for generating said control voltage based on a result of comparison of phase of a given reference signal and phase of said clock signal outputted from said variable delay circuit; and a low-pass filter for removing the high-frequency component of said control voltage to give to said voltage controlled oscillator, and
wherein a clock signal outputted by the variable delay circuit is fed back to the phase comparator via a frequency divider, said feed back is performed inside of a PLL circuit.