Inferential state machines
An extended state machine that makes use of an inference engine as the infrastructure for adding inferential capabilities to the state machine's execution. The result is a state machine that may operate on partial or disordered information, inferring intermediate states that have yet to be formally traversed. In addition, controls such as state timeouts and transition priorities allow for finer control of the state machine's execution, particularly in unexpected circumstances.
1. A processing system for providing logic states, comprising:
one or more subsystems for providing input data derived from corresponding one or more external components;
a computer in communication with the one or more subsystems and configured to provide ordered initial, intermediate, and later logic states based on corresponding initial, intermediate, and later input data to be received in order from the subsystems; and
an inference engine in communication with the computer and configured to cause the computer to directly transition from providing the initial logic state to providing the later logic state in the absence of the intermediate input datum being received by the computer.
2. A processing system according to claim 1 , wherein the inference engine is further configured to validate its inference upon later receipt of the intermediate input datum.
3. A processing system according to claim 1 , wherein the computer is further configured with at least one timeout means associated with its intermediate logic state, the timeout means configured to cause the computer to directly transition from providing the initial logic state to providing the later logic state upon expiration of a timeframe defining the timeout means and in the absence of the intermediate input datum being received by the computer.
4. A processing system according to claim 1 , wherein the computer is further configured to provide one or more of the initial, intermediate, and later logic states based on one or more conditions.
5. A processing system according to claim 4 , wherein the conditions comprise event occurrences.
6. A processing system according to claim 4 , wherein a plurality of conditions exist, and the plurality of conditions are prioritized in order to determine the logic state provided by the computer.
7. A processing system according to claim 1 , wherein the inference engine causes the computer to directly transition from providing the initial logic state to providing the later logic state using an iterative process based on the inference engine monitoring the received initial input data and the received later input data.
8. A processing system according to claim 1 , wherein the inference engine is configured to cause the direct transition of the computer from providing the initial logic state to providing the later logic state in response to a query by a client machine in communication with the processing system.
9. A processing system according to claim 8 , wherein the inference engine is configured to cause the direct transition of the computer using computer-readable instructions provided to the client machine in response to the query.
10. A method of providing logic states, the method comprising:
providing one or more external components configured to orderly generate initial, intermediate, and later input data corresponding to ordered first, second and third logic states of a computer;
receiving the initial input data by the computer;
providing a first logic state with the computer based on the received initial input data;
receiving the later input data by the computer;
inferring the third logic state from an out-of-order receipt of the later input data following the receipt of the initial input data by the computer, and in the absence of the intermediate input datum being received by the computer; and
providing the third logic state with the computer by directly transitioning from the first logic state to the third logic state based on the inference.
11. A method according to claim 10 , further comprising validating the inference upon later receipt of the intermediate input datum by the computer.
12. A method according to claim 10 , wherein providing the third logic state further comprises providing the third logic state by directly transitioning from the first logic state to the third logic state based on the inference, and further based on at least one timeout means associated with the computer's second logic state, the timeout means configured to cause the computer to directly transition from providing the initial logic state to providing the later logic state upon expiration of a timeframe defining the timeout means and in the absence of the intermediate input datum being received by the computer.
13. A method according to claim 10 , the method further comprising providing one or more of the first, second or third logic states based on one or more conditions.
14. A method according to claim 13 , wherein the conditions comprise event occurrences.
15. A method according to claim 13 , wherein a plurality of conditions exist, and the method further comprises prioritizing the plurality of conditions to determine which of the one or more first, second or third logic states is provided.
16. A method according to claim 10 , wherein providing the third logic state by directly transitioning from the first logic state to the third logic state based on the inference comprises employing an iterative process based on monitoring the received initial input data and the received later input data.
17. A method according to claim 10 , wherein inferring the third logic state and providing the third logic state occurs in response to a query by a client machine.
18. A method according to claim 17 , wherein inferring the third logic state and providing the third logic state occurs using computer-readable instructions provided to the client machine in response to the query.