IP Library Granted Patent US 7,248,526
Granted Patent B2
US 7,248,526 · App. 11/180,552 · Granted Jul 24, 2007

Refresh period generating circuit

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Quick Facts
Patent No.
US 7,248,526
App. No.
11/180,552
Granted
Jul 24, 2007
Kind
B2
Abstract

A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

Claims (27)

1. A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising:

an oscillation circuit which oscillates at an oscillating frequency with temperature dependence on ambient temperature;

a dividing circuit which divides an oscillation output of said oscillation circuit and outputs signals having a plurality of different frequencies;

a temperature detector which detects said ambient temperature; and

a selector which switches and selects among the signals of said dividing circuit based on an output of said temperature detector, and outputs a signal as a reference of said refresh period,

wherein

said oscillating frequency of said oscillation circuit has substantially said temperature dependence at least within a range from a first temperature point to a second temperature point lower than said first temperature point,

and wherein said selector selects and outputs a signal of said dividing circuit having a frequency depending on said temperature dependence of analog form when said temperature detector detects a temperature within a range from said first temperature point to said second temperature point,

selects and outputs one or more signals of said dividing circuit each having a frequency higher than said frequency depending on said temperature dependence of analog form when said temperature detector detects a temperature higher than said first temperature point, and

selects and outputs one or more signals of said dividing circuit, each having a frequency lower than said frequency depending on said temperature dependence of analog form when said temperature detector detects a temperature lower than said second temperature point.

2. A refresh period generating circuit, which generates a refresh period in refreshing a DRAM cell, comprising:

an oscillation circuit which oscillates at an oscillating frequency with temperature dependence on ambient temperature;

a dividing circuit which divides an oscillation output of said oscillation circuit and outputs signals having a plurality of different frequencies;

a temperature detector which detects said ambient temperature; and

a selector which switches and selects among the signals of said dividing circuit based on an output of said temperature detector, and outputs a signal as a reference of said refresh period,

wherein said oscillating frequency of said oscillation circuit has substantially said temperature dependence at least within a range from a first temperature point to a second temperature point lower than said first temperature point,

and wherein in said selector, one or more switching temperature points are set, selection is performed such that a signal of higher temperature has a frequency higher than that of a signal of lower temperature at each switching temperature point, and all said switching temperature points are not included within a range from said first temperature point to said second temperature point.

3. A refresh period generating circuit according to claim 1 or 2 ,

wherein a temperature range higher than said first temperature point is regarded as an oscillation range of 77% or more of a maximum oscillating frequency, and a temperature range lower than said temperature point is regarded as an oscillation range of 130% or less of a minimum oscillating frequency.

4. A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising:

an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature;

a dividing circuit which divides an oscillation output of said oscillation circuit and outputs signals having a plurality of different frequencies;

a temperature detector which detects said ambient temperature; and

a selector which switches and selects among the signals of said dividing circuit based on an output of said temperature detector, and outputs a signal as a reference of said refresh period,

wherein said temperature dependence in said oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of said predetermined temperature range,

wherein said selector switches said division outputs out of said predetermined temperature range,

and wherein a region of high temperatures out of said predetermined temperature range is regarded as an oscillation range of 77% or more of a maximum oscillating frequency, and a region of low temperatures out of said predetermined temperature range is regarded as an oscillation range of 130% or less of a minimum oscillating frequency.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: LONGITUDE SEMICONDUCTOR S.A.R.L.
To: LONGITUDE LICENSING LIMITED
Reel/Frame 046867/0248 →
CHANGE OF NAME Recorded Aug 24, 2016
From: PS5 LUXCO S.A.R.L.
To: LONGITUDE SEMICONDUCTOR S.A.R.L.
Reel/Frame 039793/0880 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2016
From: PS4 LUXCO S.A.R.L.
To: PS5 LUXCO S.A.R.L.
Reel/Frame 039818/0506 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2014
From: ELPIDA MEMORY, INC.
To: PS4 LUXCO S.A.R.L.
Reel/Frame 032899/0588 →
SECURITY AGREEMENT Recorded Jul 29, 2013
From: PS4 LUXCO S.A.R.L.
To: ELPIDA MEMORY INC.
Reel/Frame 032414/0261 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2005
From: ITO, YUTAKA; ODAIRA, NOBUHIRO
To: ELPIDA MEMORY, INC.
Reel/Frame 016759/0676 →