IP Library Granted Patent US 7,233,534
Granted Patent B2
US 7,233,534 · App. 11/180,733 · Granted Jun 19, 2007

Electronic circuit package

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Quick Facts
Patent No.
US 7,233,534
App. No.
11/180,733
Granted
Jun 19, 2007
Kind
B2
Abstract

An electronic apparatus which includes a wiring substrate which includes wiring conductors, and a plurality of semiconductor bare chips that are formed on the wiring substrate. The semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor.

Claims (10)

1. An electronic apparatus comprising:

a wiring substrate which includes wiring conductors; and

a plurality of semiconductor bare chips that are formed on said wiring substrate,

wherein said semiconductor bare chips include a processor for processing data and a circuit having a checking function for detecting faults of the processor, and

wherein said processor and said circuit are each formed in a bare chip.

2. An electronic apparatus according to claim 1 , wherein said wiring substrate is a multilayer wiring substrate.

3. An electronic apparatus according to claim 2 , wherein said multilayer wiring substrate is a ceramic substrate.

4. An electronic apparatus according to claim 1 , wherein a semiconductor bare chip corresponding to said circuit are connected respectively with said wiring substrate by wire bonding.

5. An electronic apparatus according to claim 1 , wherein the checking function of said circuit is a watch dog timer for resetting said processor when faults of said processor are detected.

6. An electronic apparatus according to claim 1 , wherein at least one of said semiconductor bare chips is a memory for storing data.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2009
From: HITACHI, LTD.
To: RISING SILICON, INCORPORATED
Reel/Frame 023486/0530 →