IP Library Granted Patent US 7,402,500
Granted Patent B2
US 7,402,500 · App. 11/181,607 · Granted Jul 22, 2008

Methods of forming shallow trench isolation structures in semiconductor devices

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Quick Facts
Patent No.
US 7,402,500
App. No.
11/181,607
Granted
Jul 22, 2008
Kind
B2
Abstract

Methods of forming a shallow trench isolation structures in semiconductor devices are disclosed. A disclosed method comprises forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate; forming a trench defining first and second active areas by etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area; forming a third oxide layer along an inside of the trench; forming a fourth oxide layer to fill up the trench; forming a sacrificial oxide layer on the fourth oxide layer; and removing the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer so as to form the shallow trench isolation. Thus, it is possible to minimize the damage of a narrow active area when forming an element isolation area through an STI process.

Claims (14)

1. A method of forming a shallow trench isolation structure in a semiconductor device comprising:

forming a first oxide layer, a nitride layer, and a second oxide layer above a substrate;

etching the second oxide layer, the nitride layer, the first oxide layer, and the substrate in a predetermined area to form a trench defining first and second active areas;

forming a third oxide layer inside of the trench;

filling the trench with a fourth oxide layer;

forming a photoresist pattern above the fourth oxide layer in an area corresponding to the first active area;

forming a sacrificial oxide layer over a resulting structure including over the photoresist pattern; and

removing the photoresist pattern, the sacrificial oxide layer, the fourth oxide layer, the third oxide layer, the second oxide layer, and the nitride layer.

2. A method as defined in claim 1 , wherein the sacrificial oxide layer is formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

3. A method as defined in claim 2 , wherein the PECVD method comprises injecting SiH 4 gas or TEOS gases, and O 2 gas into a PECVD equipment at a temperature of about 180˜220° C.

4. A method as defined in claim 1 , wherein the third oxide layer has a thickness of about 10˜100 Å.

5. A method as defined in claim 1 , wherein the sacrificial oxide layer, the fourth oxide layer, the, third oxide layer, and the second oxide layer are removed by blanket etching.

6. A method as defined in claim 1 , wherein the nitride layer is removed by a chemical mechanical polishing process.

7. A method as defined in claim 6 , further comprising performing an etching process using a acid (H 3 PO 4 ) after performing the chemical mechanical polishing process.

Assignments (2)
CHANGE OF NAME Recorded Sep 7, 2007
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 019800/0147 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2005
From: LEE, JAE SUK
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016782/0518 →