IP Library Granted Patent US 7,501,311
Granted Patent B2
US 7,501,311 · App. 11/183,833 · Granted Mar 10, 2009

Fabrication method of a wafer structure

Assignee: Advanced Semiconductor Engineering, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,501,311
App. No.
11/183,833
Granted
Mar 10, 2009
Kind
B2
Abstract

A wafer fabricating method at least includes the steps of providing a wafer having an active surface with a plurality of pads, forming a plurality of bumps on the pad, and forming an organic protective layer on the bump and the active surface. Besides improving the quality of the wafer, the wafer structure according to the invention is oxidation-resistant, thus avoiding the cold-joint problem when soldered to the substrate.

Claims (31)

1. A fabricating method of a flip-chip package, comprising the steps of:

providing a chip having an active surface, wherein the active surface has a plurality of bumps;

forming an organic protective layer on the bumps and the active surface;

removing the organic protective layer disposed on the chips by a flux, wherein the organic protective layer prevents the bump from being oxidized until the flux is applied thereon; and

soldering the chip onto a substrate after the organic protective layer of the chip has been removed.

2. The fabricating method according to claim 1 , wherein the step of using a flux to remove the organic protective layer further comprises:

applying a flux on the substrate;

overturning the chip on the substrate, so that the organic protective layer disposed on the bumps contacts the substrate; and

dissolving the organic protective layer by the flux.

3. The fabricating method according to claim 1 , wherein the step of using a flux to remove the organic protective layer further comprises:

draping a flux on the surface of the bump;

dissolving the organic protective layer by the flux; and

overturning the chip on the substrate, so that the organic protective layer disposed on the bumps contacts the substrate.

4. The fabricating method according to claim 1 , wherein the organic protective layer is a layer of organic solderability preservatives (OSP).

5. The fabricating method according to claim 1 , wherein the thickness of the organic protective layer ranges from 1000˜2000 Å.

6. The fabricating method according to claim 1 , wherein the thickness of the organic protective layer is 1500 Å.

7. The fabricating method according to claim 1 , wherein the bumps are made of copper.

8. The fabricating method according to claim 1 , wherein the bumps are made of lead-tin alloy.

9. A fabricating method of a flip-chip package, comprising the steps of:

(a) providing a chip having an active surface, wherein the active surface has a plurality of bumps;

(b) forming an organic protective layer on the bumps and the active surface;

(c) applying a flux on the substrate;

(d) overturning the chip on the substrate after the organic protective layer and the flux are formed on the bumps and the substrate respectively, so that the organic protective layer disposed on the bumps contacts with the flux applied on the substrate; and

(e) dissolving the organic protective layer on the bumps by the flux on the substrate after the organic protective layer formed on the bumps contacts with the flux applied on the substrate; and

(f) soldering the chip onto a substrate after the organic protective layer is dissolved by the flux, wherein the step (f) of soldering the chip onto the substrate is performed after the steps of (b), (c), (d) and (e).

10. The fabricating method according to claim 9 , wherein the bumps are made of copper.

11. The fabricating method according to claim 9 , wherein the bumps are made of lead-tin alloy.

12. The fabricating method according to claim 9 , wherein the organic protective layer is a layer of organic solderability preservatives (OSP).

13. The fabricating method according to claim 9 , wherein a thickness of the organic protective layer ranges from 1000˜2000 Å.

14. The fabricating method according to claim 9 , wherein a thickness of the organic protective layer is 1500 Å.

15. The fabricating method according to claim 9 , wherein the step of forming the organic protective layer is selected from group consisting rotary coating, physical and chemical depositing, printing, draping or spraying.

Assignments (2)
CONFIRMATORY LICENSE Recorded Feb 25, 2020
From: DUKE UNIVERSITY
To: NATIONAL INSTITUTES OF HEALTH (NIH), U.S. DEPT. OF HEALTH AND HUMAN SERVICES (DHHS), U.S. GOVERNMENT
Reel/Frame 052885/0845 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2005
From: TSAI, CHI-LONG
To: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
Reel/Frame 016787/0085 →
Priority Claims (1)
TW 93133451 A · Nov 3, 2004 · national
Continuity (1)
Related Publication 20060094223A1 · May 4, 2006