Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions
The invention includes semiconductor constructions having trenched isolation regions. The trenches of the trenched isolation regions can include narrow bottom portions and upper wide portions over the bottom portions. Electrically insulative material can fill the upper wide portions while leaving voids within the narrow bottom portions. The bottom portions can have substantially vertical sidewalls, and can join to the upper portions at steps which extend substantially perpendicularly from the sidewalls. The trenched isolation regions can be incorporated into a memory array, and/or can be incorporated into an electronic system. The invention also includes methods of forming semiconductor constructions.
1 . A semiconductor construction, comprising:
a semiconductor substrate;
a trench extending into the substrate; the trench comprising a narrow bottom portion and an upper wide portion over the bottom portion and joining the bottom portion at a step; and
a substantially solid electrically insulative material substantially filling the trench.
2 . The construction of claim 1 wherein the upper portion is at least about twice as wide as the bottom portion.
3 . The construction of claim 1 wherein the bottom portion has a substantially vertical sidewall, and wherein the step extends substantially perpendicularly to the sidewall.
4 . The construction of claim 1 further comprising a void within the substantially solid insulative material; said void being at least substantially entirely within the bottom portion of the trench.
5 . The construction of claim 4 wherein the void is a gaseous region.
6 . The construction of claim 4 wherein the void is entirely within the bottom portion of the trench.
7 - 9 . (canceled)
10 . A semiconductor construction comprising a plurality of trenched regions having narrow bottom portions and upper wide portions over the bottom portions, said trenched regions also having voids retained at least substantially entirely within the bottom portions.
11 - 12 . (canceled)
13 . The construction of claim 10 wherein the voids are gaseous regions.
14 . The construction of claim 10 wherein said trenched regions are trenched isolation regions.
15 . The construction of claim 14 further comprising transistor devices adjacent the isolation regions.
16 . The construction of claim 15 wherein at least some of the transistor devices having source/drain regions that elevationally overlap the voids.
17 . The construction of claim 16 wherein the isolation regions comprise electrically insulative material within the top and bottom portions.
18 - 22 . (canceled)
23 . A memory array, comprising:
a plurality of transistors over a semiconductor substrate, the transistors comprising gates and source/drain regions adjacent the gates;
a plurality of charge storage devices electrically coupled with some of the source/drain regions; and
a plurality of isolation regions extending within the substrate and providing electrical isolation for at least some of the transistors; at least some individual isolation regions comprising lower narrow portions joining to upper wide portions at steps, comprising substantially solid insulative material within the narrow portions and wide portions, and comprising voids substantially entirely contained within the narrow portions.
24 - 25 . (canceled)
26 . The memory array of claim 23 wherein at least some of the upper wide portions are at least about twice as wide as the bottom narrow portions they are joined to.
27 . The memory array of claim 23 wherein at least some of the bottom narrow portions have substantially vertical sidewalls, and wherein at least some of the steps extend substantially perpendicularly to such sidewalls.
28 . The memory array of claim 23 wherein the substantially solid electrically insulative material comprises silicon dioxide.
29 . (canceled)
30 . The memory array of claim 23 wherein at least some of the source/drain regions are adjacent individual voids and elevationally overlap such individual voids.
31 . (canceled)
32 . The memory array of claim 23 wherein the voids are gaseous regions.
33 . An electronic system, comprising:
a processor;
a memory device in data communication with the processor; and
wherein at least one of the memory device and the processor includes one or more electrical isolation regions comprising lower narrow portions joining to upper wide portions at steps, comprising a non-gaseous material within the narrow portions and wide portions, and comprising voids substantially entirely contained within the narrow portions.
34 . The electronic system of claim 33 wherein the voids are gaseous regions.
35 . The electronic system of claim 33 further comprising transistors adjacent at least some of the electrical isolation regions.
36 . The electronic system of claim 33 further comprising programmable memory devices adjacent at least some of the electrical isolation regions.
37 and 38 . (canceled)
39 . The electronic system of claim 33 wherein the non-gaseous material is a substantially solid electrically insulative material.
40 . The electronic system of claim 39 wherein the substantially solid electrically insulative material comprises silicon dioxide.
41 . A method of forming a semiconductor construction, comprising:
providing a semiconductor substrate;
forming a first opening extending into the substrate, the first opening having a first width;
forming a second opening extending downwardly into the substrate from the first opening, the second opening having a second width which is less than the first width; and
forming electrically insulative material within the first and second openings, the electrically insulative material substantially filling the first opening and leaving a void within the second opening.
42 . The method of claim 41 wherein the first width is at least about twice as wide as the second width.
43 . The method of claim 41 further comprising forming a masking material within the first opening to define a location for the second opening, and wherein the second opening is formed while the masking material is within the first opening.
44 . The method of claim 41 wherein the electrically insulative material comprises silicon dioxide.
45 . The method of claim 41 wherein the first opening is formed to a depth of at least about 1 micron within the substrate.
46 . A method of forming a semiconductor construction, comprising:
providing a semiconductor substrate;
forming a pair of openings extending into the substrate, the individual openings having an upper portion of a first width and a lower portion of a second width less than the first width, with the first and second width portions joining at a step; the openings being spaced from one another by a region of the semiconductor substrate;
forming electrically insulative material within the openings; the electrically insulative material substantially filling the upper portions of the openings and leaving voids within the lower portions of the openings; and
forming a transistor having a gate over said region of the semiconductor substrate.
47 . The method claim 46 wherein the transistor gate is floating gate, and further comprising forming a control gate over the floating gate.
48 . The method claim 46 wherein the upper portions of the openings are at least about twice as wide as the lower portions.
49 . The method claim 46 wherein the lower portions have substantially vertical sidewalls, and wherein the steps extend substantially perpendicularly to such sidewalls.
50 . The method claim 46 wherein the electrically insulative material comprises silicon dioxide.