Semiconductor device and method for manufacturing the same
View Patent ↗An exemplary method for manufacturing a semiconductor device includes: forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer, respectively formed thereabove and one or more junction regions formed therein so as to fill a full height of a gap between gates; forming a contact hole partially exposing the junction region(s) by etching the insulating layer; and selectively forming a silicon layer on an exposed portion of the junction region at a bottom of the contact hole.
1. A method for manufacturing a semiconductor device comprising:
forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer thereabove and a junction region therein so as to fill a fill height of a gap between gates;
forming a first contact hole partially exposing the junction region and a second contact hole exposing the gate by etching the insulating layer;
overetching the insulating layer sufficiently to provide the first contact hole with an overcut profile; and
selectively growing an epitaxial silicon layer on an exposed portion of the junction region at a bottom of the first contact hole using a mask exposing only the junction region.
2. A method for manufacturing a semiconductor device comprising:
forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer thereabove and a junction region therein so as to fill a full height of a gap between gates;
forming a first contact hole partially exposing the junction region and a second contact hole exposing the gate by etching the insulating layer; and
selectively forming a silicon layer on an exposed portion of the junction region at a bottom of the first contact hole.
3. A method for manufacturing a semiconductor device comprising:
forming an insulating layer over a semiconductor substrate having a gate insulating layer, a gate, and a spacer thereabove and a junction region therein so as to fill a full height of a gap between gates;
forming a first contact hole partially exposing the junction region by etching the insulating layer;
selectively forming a silicon layer on an exposed portion of the junction region at a bottom of the first contact hole using a mask exposing only the junction region.
4. The method of claim 2 , wherein selectively forming the silicon layer comprises epitaxially growing the silicon layer.
5. The method of claim 2 , wherein etching the insulating layer comprises overetching the insulating layer sufficiently to provide the first contact hole with an overcut profile.
6. The method of claim 3 , wherein:
selectively forming the silicon layer comprises epitaxially growing the silicon layer; and
etching the insulating layer comprises overetching the insulating layer sufficiently to provide the first contact hole with an overcut profile.
7. The method of claim 3 , wherein:
selectively forming the silicon layer comprises epitaxially growing the silicon layer; and
etching the insulating layer further comprises forming a second contact hole exposing the gate.
8. The method of claim 3 , wherein etching the insulating layer comprises:
overetching the insulating layer sufficiently to provide the first contact hole with an overcut profile; and
forming a second contact hole exposing the gate.
9. The method of claim 2 , wherein:
forming the silicon layer comprises epitaxially growing the silicon layer; and
etching the insulating layer comprises overetching the insulating layer sufficiently to provide the first contact hole with an overcut profile.
10. The method of claim 2 , wherein selectively forming the silicon layer further comprises forming a mask exposing only the junction region.
11. The method of claim 1 , further comprising forming a mask exposing only the junction region.
12. The method of claim 2 , further comprising forming a mask exposing only the junction region.
13. The method of claim 1 , further comprising forming the gate insulating layer, gate, and spacer on the semiconductor substrate, and forming a plurality of junction regions in the semiconductor substrate.
14. The method of claim 2 , further comprising forming the gate insulating layer, gate, and spacer on the semiconductor substrate, and forming a plurality of junction regions in the semiconductor substrate.
15. The method of claim 3 , further comprising forming the gate insulating layer, gate, and spacer on the semiconductor substrate, and forming a plurality of junction regions in the semiconductor substrate.