Resin-molded package with cavity structure
View Patent ↗A package includes: a substrate having a ridged peripheral portion and a center portion defined by and lower in level than the ridged peripheral portion. A semiconductor chip is mounted on the center portion. A plurality of lead is electrically coupled to the semiconductor chip and penetrates the substrate outwardly from the center portion. The package also includes a cap defining a cavity space which accommodates the semiconductor chip. The cap has a cap bonding face bonded with a substrate bonding face of the ridged peripheral portion. The cap bonding face and the substrate bonding face are higher in level than the center portion.
1. A semiconductor package comprising:
a substrate having a sidewall, said sidewall surrounding a central portion of said substrate;
a semiconductor chip mounted on said substrate; and
a cap bonded to an upper surface of said side wall,
wherein all bonding surfaces between the sidewall and the cap are sloped to one direction.
2. The semiconductor package according to claim 1 , further comprising a plurality of leads electrically coupled to said semiconductor chip, each of said plurality of leads penetrating said substrate and extending out of said substrate.
3. The semiconductor package according to claim 1 , wherein said cap defines a cavity space, which accommodates said semiconductor chip.
4. The semiconductor package as claimed in claim 1 , wherein said substrate has a substrate bonding face and said cap has a cap bonding face, each of said cap bonding face and said substrate bonding face comprises an inwardly sloped-down plane surface which extends annularly.
5. The semiconductor package as claimed in claim 1 , wherein said substrate has a substrate bonding face and said cap has a cap bonding face, each of said cap bonding face and said substrate bonding face comprises an outwardly sloped down plane surface which extends annularly.
6. The semiconductor package as claimed in claim 1 , wherein said cap has a cap bonding face, said cap comprising a flat body and a peripheral portion which has said cap bonding face.
7. The semiconductor package as claimed in claim 1 , wherein said plurality of leads are four in number and each of said four leads extends radially and outwardly from said substrate, so that each lead is spaced substantially 90° from an adjacent one of said four leads.
8. The semiconductor package as claimed in claim 1 , wherein said bonding surfaces are sloped inwardly toward said semiconductor chip.
9. The semiconductor package as claimed in claim 1 , wherein said bonding surfaces are sloped outwardly away from said semiconductor chip.
10. A semiconductor package comprising:
a substantially cup-shaped substrate having a central portion and a sidewall surrounding said central portion;
a semiconductor chip mounted on a top surface of said central portion; and
a cap bonded to an upper surface of said side wall,
wherein all bonding surfaces between the sidewall and the cap are sloped to one direction.
11. The semiconductor package according to claim 10 , wherein all said bonding surfaces between the sidewall and the cap comprise inwardly slopeddown surfaces.
12. The semiconductor package according to claim 11 , wherein said inwardly sloped-down surfaces extend annularly.
13. The semiconductor package according to claim 10 , wherein all said bonding surfaces between the sidewall and the cap comprise outwardly sloped-down surfaces.
14. The semiconductor package according to claim 13 , wherein said outwardly sloped-down surfaces extend annularly.
15. The semiconductor package according to claim 10 , further comprising a plurality of leads electrically coupled to said semiconductor chip, each of said plurality of leads penetrating said substrate and extending out of said substrate and coplanar with a bottom surface of said central portion.