Semiconductor device and fabrication method thereof
View Patent ↗A semiconductor device and a fabrication method thereof in which the semiconductor device includes capacitors having a metal/insulator/metal (MIM) structure are disclosed. The method includes forming an interlayer insulating film on a structure of a semiconductor substrate that exposes lower wiring and a lower insulating film; selectively etching the interlayer insulating film to form a first electrode opening that exposes the lower wiring; forming a first electrode in the first electrode opening such that the first electrode opening is filled; selectively etching the interlayer insulating film at a region of the same adjacent to the first electrode to thereby form a second electrode opening; forming a dielectric layer along inner walls that define the second electrode opening; forming a second electrode on the dielectric layer in such a manner to fill the second electrode opening; and forming upper wiring on at least a portion of the second electrode.
1. A semiconductor device comprising:
a substrate comprising a first wire;
a first electrode of a capacitor on and in contact with an uppermost horizontal surface of the first wire;
a second electrode of the capacitor on the substrate horizontally adjacent to the first electrode and having an uppermost horizontal surface that is coplanar with an uppermost horizontal surface of the first electrode;
a dielectric layer between the first electrode and the second electrode to form a capacitance in a horizontal direction; and
a second wire on and in contact with the uppermost horizontal surface of the second electrode.
2. The semiconductor device as claimed in claim 1 , wherein each of the first and second electrodes has a top view in shape of a comb having a plurality of recess and concave patterns.
3. The semiconductor device as claimed in claim 2 , wherein the recess patterns of the first electrode are formed face to face with the concave patterns of the second electrode, and the concave patterns of the first electrode are formed face to face with the recess patterns of the second electrode.
4. The semiconductor device as claimed in claim 2 , wherein the first and second electrodes have walls facing each other, each wall having the plurality of recess and concave patterns.
5. The semiconductor device as claimed in claim 4 , wherein the recess patterns of the first electrode are face to face with the concave patterns of the second electrode, and the concave patterns of the first electrode are face to face with the recess patterns of the second electrode.
6. The semiconductor device as claimed in claim 1 , wherein the dielectric layer comprises a multi-layered structure having at least two layers.
7. The semiconductor device as claimed in claim 1 , wherein the dielectric layer includes a silicon oxide layer and a nitride layer.
8. The semiconductor device as claimed in claim 1 , wherein the dielectric layer is at opposite sides and a lower surface of the second electrode.
9. The semiconductor device as claimed in claim 1 , wherein the first and second electrodes comprise copper.
10. The semiconductor device as claimed in claim 1 , wherein the recess patterns of the first electrode are face to face with the concave patterns of the second electrode, and the concave patterns of the first electrode are face to face with the recess patterns of the second electrode.
11. The semiconductor device as claimed in claim 1 , wherein the first electrode is on the lower wire and the lower insulating layer adjacent to the lower wire.
12. The semiconductor device as claimed in claim 1 , wherein the first and second electrodes are on the same layer and comprise an identical material.
13. The semiconductor device as claimed in claim 1 , wherein the capacitor comprises the first and second electrodes.
14. The semiconductor device of claim 1 , wherein the lowermost horizontal surface of the second electrode is not coplanar with the lowermost horizontal surface of the first electrode.