System and method for providing digital pulse width modulation
View Patent ↗A pulse width modulation system for use in a switching power supply circuit provides high-resolution pulse width modulated signals. The pulse width modulation system is configured to receive a control signal comprising a (m+n)-bit binary word and to provide a pulse width modulated signal with a predetermined average duty cycle having a resolution of substantially 2 −(m+n) . The pulse width modulation system includes a timing circuit for providing 2 m timing signals, a dithering circuit, and a signal generator. Upon receiving the control signal, the dithering circuit is configured to provide a modified control signal, which comprises a series of up to 2 n m-bit binary words. The signal generator is configured to receive the timing signals and the modified control signal and to provide the pulse width modulated signal having a duty cycle, which, when averaged over 2 n timing cycles, is approximately equal to the predetermined average duty cycle. The pulse width modulated signal is used by a switching power supply circuit to control at least one power switching device.
1. In a switching power supply system having at least one switching element, a control circuit for driving said at least one switching element comprises:
a dithering circuit adapted to receive a control signal comprising a (m+n)-bit binary word, where m and n are positive integers, and to provide a modified control signal;
a timing circuit adapted to provide 2 m timing signals and to communicate at least one of said timing signals to said dithering circuit; and
a signal generator adapted to receive said modified control signal and said timing signals and to provide a pulse width modulated signal to said at least one switching element, said pulse width modulated signal activating said at least one switching element with an average duty cycle that relates to the (m+n)-bit binary word divided by 2 (m+n) .
2. The control circuit of claim 1 , wherein said dithering circuit is adapted to calculate said modified control signal.
3. The control circuit of claim 2 , wherein said dithering circuit includes an n-bit binary adder circuit, an n-bit delay circuit, and an m-bit binary adder circuit, said n-bit binary adder having first input operand terminals for receiving n least significant bits of said control signal, second input operand terminals, output sum terminals being coupled with said second input operand terminals via said n-bit delay circuit, and a carry terminal, said n-bit delay circuit being activated by said at least one of said timing signals, said m-bit binary adder circuit having first input operand terminals for receiving m most significant bits of said control signal, second input operand terminals being coupled with said carry terminal, and output terminals for providing said modified control signal.
4. The control circuit of claim 1 , wherein said each of said timing signals comprises a voltage pulse having a predetermined period during each timing cycle of the timing circuit, said timing cycle being substantially equal to 2 m of said predetermined periods.
5. The control circuit of claim 4 , wherein said timing signals provide said voltage pulses in accordance with a predetermined sequence.
6. The control circuit of claim 1 , wherein said timing circuit comprises a ring oscillator.
7. The control circuit of claim 1 , wherein said timing circuit includes a delay line and an inverter circuit, said delay line having an input terminal and an output terminal respectively coupled with an output terminal and an input terminal of said inverter circuit.
8. The control circuit of claim 7 , wherein said delay line comprises at least 2 m delay elements.
9. The control circuit of claim 6 , wherein said delay elements comprise buffer circuits.
10. The control circuit of claim 6 , wherein said delay elements comprise inverter circuits.
11. The control circuit of claim 6 , wherein each of said delay elements is adapted to provide a delay period that is less than or substantially equal to ten nanoseconds.
12. The control circuit of claim 1 , wherein said signal generator is adapted to provide said pulse width modulated signal with a phase shift.
13. The control circuit of claim 12 , wherein said phase shift is preprogrammed.
14. The control circuit of claim 12 , wherein said phase shift is programmable.
15. The control circuit of claim 1 , wherein said signal generator includes a latch system for providing said pulse width modulated signal.
16. The control circuit of claim 15 , wherein said latch system is adapted to provide said pulse width modulated signal with a first signal state upon receiving a first timing signal and with a second signal state upon receiving said second timing signal.
17. The control circuit of claim 16 , wherein said first signal state is associated with a high logic level, and said second signal state is associated with a low logic level.
18. The control circuit of claim 16 , wherein said signal generator further includes a multiplexer circuit configured to receive said modified control signal and to select said second timing signal.
19. The control circuit of claim 16 , wherein said signal generator further includes a first multiplexer circuit configured to receive a phase signal and to select said first timing signal and a second multiplexer circuit configured to receive a sum of said phase signal and said modified control signal and to select said second timing signal.
20. The control circuit of claim 19 , wherein said phase signal comprises an m-bit binary word.
21. The control circuit of claim 19 , wherein said signal generator further includes a memory system for providing said phase signal.
22. A method for providing pulse width modulated signals, comprising:
receiving a control signal comprising a (m+n)-bit binary word, where m and n are positive integers;
dithering said control signal to provide a modified control signal;
providing 2 m timing signals; and
generating a pulse width modulated signal with an average duty cycle that relates to the (m+n)-bit binary word divided by 2 (m+n) .
23. The method of claim 22 , wherein said dithering said control signal comprises calculating said modified control signal.
24. The method of claim 22 , wherein said providing said timing signals comprises providing each of said timing signals as a voltage pulse having a predetermined period during each timing cycle of the timing circuit, said timing cycle being substantially equal to 2 m of said predetermined periods.
25. The method of claim 24 , wherein said providing said timing signals comprises providing said voltage pulses in accordance with a predetermined sequence.
26. The method of claim 22 , wherein said generating said pulse width modulated signal includes phase shifting said pulse width modulated signal.