Method for forming a semiconducting layer with improved gap filling properties
View Patent ↗A method of manufacturing a memory device includes forming a first dielectric layer over a substrate, forming a charge storage element over the first dielectric layer and forming an inter-gate dielectric over the charge storage element. The method also includes depositing a silicon control gate layer over the inter-gate dielectric using a reactant that contains chlorine.
1. A method of manufacturing a memory device, the method comprising:
forming a first dielectric layer over a substrate;
forming a charge storage element over the first dielectric layer in one layer;
forming an inter-gate dielectric over and directly contacting the first dielectric layer and the charge storage element, where the inter-gate dielectric includes a plurality of layers;
depositing a polysilicon layer directly over the inter-gate dielectric, where depositing the polysilicon control gate layer includes:
providing a SiH 2 Cl 2 reactant to a deposition chamber at a first flow rate, and
providing a SiH 4 reactant to the deposition chamber at a second flow rate,
where the SiH 2 Cl 2 and SiH 4 reactants are concurrently provided to the deposition chamber,
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate; and
forming a contact hole in the interlayer dielectric.
2. The method of claim 1 , where the providing the SiH 2 Cl 2 and SiH 4 reactants comprises:
providing the SiH 2 Cl 2 and SiH 4 reactants to the deposition chamber at approximately a same flow rate.
3. The method of claim 1 , where each of the first and second flow rates ranges from about 100 standard cubic centimeters per minute (sccm) to about 10,000 sccm.
4. The method of claim 1 , where a ratio of the first flow rate to the second flow rate ranges from approximately 1:10 to approximately 10:1.
5. The method of claim 1 , where providing the SiH 2 Cl 2 and SiH 4 reactants includes:
providing the SiH 2 Cl 2 and SiH 4 reactants, into the deposition chamber, for a period of time ranging from about 60 seconds to about 3,600 seconds to produce the polysilicon control gate layer at a thickness ranging from about 500 Å to about 3,000 Å.
6. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming a plurality of charge storage structures over the first dielectric layer, where each of the plurality of charge storage structures is formed in one layer;
forming an inter-gate dielectric over and directly contacting along a longitudinal length of the first dielectric layer and the plurality of charge storage structures, where the inter-gate dielectric includes an oxide-nitride-oxide stack, and where an opening is formed between adjacent ones of the charge storage structures; and
depositing a polysilicon layer directly over the inter-gate dielectric using a chemical vapor deposition process, the polysilicon layer filling the opening, where the step of depositing comprises:
providing a SiH 2 Cl 2 reactant to a deposition chamber at a first flow rate under a pressure greater than 1 Torr, and
providing a SiH 4 reactant to the deposition chamber at a second flow rate under a pressure greater than 1 Torr,
where a ratio of the first flow rate to the second flow rate ranges from approximately 1:10 to approximately 10:1,
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate; and
forming a contact hole in the interlayer dielectric.
7. The method of claim 6 , where providing the SiH 2 Cl 2 and SiH 4 reactants comprises:
concurrently providing the SiH 2 Cl 2 and SiH 4 reactants to the deposition chamber at approximately a same flow rate.
8. The method of claim 6 , where the first and second flow rates each range from about 100 standard cubic centimeters per minute (sccm) to about 10,000 sccm.
9. The method of claim 6 , where the chemical vapor deposition process comprises heating the deposition chamber to a temperature ranging from about 450° C. to about 800° C.
10. The method of claim 6 , where SiH 4 and SiH 2 Cl 2 reactants of the polysilicon layer has a thickness ranging from about 50Å to 500Å.
11. The method of claim 6 , providing the SiH 2 Cl 2 and SiH 4 reactants comprises:
concurrently providing the SiH 2 Cl 2 and SiH 4 reactants to the deposition chamber.
12. The method of claim 6 , where providing the SiH 2 Cl 2 and SiH 4 reactants includes:
providing the SiH 2 Cl 2 and SiH 4 reactants, into the deposition chamber, for a period of time ranging from about 60 seconds to about 3,600 seconds to produce the polysilicon layer at a thickness ranging from about 500 Å to about 3,000 Å.
13. A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate;
forming a plurality of charge storage structures over the first dielectric layer, where each of the plurality of charge storage structures is formed in one layer;
forming an inter-gate dielectric over and directly contacting along a longitudinal length of the first dielectric layer and the plurality of charge storage structures, where the inter-gate dielectric includes a layer of silicon nitride between first and second layers of silicon oxide, and where an opening is formed between adjacent ones of the charge storage structures; and
depositing a polysilicon layer over the inter-gate dielectric, the polysilicon layer filling the opening, where the depositing comprises:
depositing, under a pressure greater than 1 Torr, at least a portion of the polysilicon layer by concurrently providing SiH 2 Cl 2 and SiH 4 reactants to a deposition chamber at first and second flow rates, respectively,
where a ratio of the first flow rate to the second flow rate ranges from approximately 1:10 to approximately 10:1,
planarizing the polysilicon layer to form a control gate;
forming an interlayer dielectric on the control gate; and
forming a contact hole in the interlayer dielectric.
14. The method of claim 13 , where the depositing at least a portion of the polysilicon layer comprises:
depositing a first portion of the polysilicon layer using SiH 4 and Cl 2 as reactants or using SiH 4 and HCl as reactants, and
terminating flow of Cl 2 or HCl after the first portion of the polysilicon layer is deposited, wherein the depositing the polysilicon layer further comprises:
depositing a second portion of the polysilicon layer using SiH 4 as a reactant.
15. The method of claim 13 , where depositing at least the portion of the polysilicon layer includes:
providing the SiH 2 Cl 2 and SiH 4 reactants, into the deposition chamber, for a period ranging from about 60 seconds to about 3,600 seconds to produce the polysilicon layer at a thickness ranging from about 500 Å to about 3,000 Å.