IP Library Granted Patent US 7,582,950
Granted Patent B2
US 7,582,950 · App. 11/190,011 · Granted Sep 1, 2009

Semiconductor chip having gettering layer, and method for manufacturing the same

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Quick Facts
Patent No.
US 7,582,950
App. No.
11/190,011
Granted
Sep 1, 2009
Kind
B2
Abstract

In a semiconductor chip A wherein an element layer 2 having transistors and the like is formed on the front face, and the back face is joined to an underlying member, such as a package substrate, the thickness T is made 100 μm or less, and thereafter, a gettering layer 3 is formed on the back face of the semiconductor chip A. The gettering layer 3 is formed, for example, by polishing the back face of said semiconductor chip A using a polishing machine. Thereby, the yield of devices can be improved in the step for assembling the package.

Claims (20)

1. A semiconductor device comprising:

a semiconductor chip which includes an element layer formed on a front face of the semiconductor chip and a gettering layer on a back face of the semiconductor chip;

a package substrate which faces the back face; and

a resin covering the semiconductor chip and the package substrate,

wherein a thickness of said semiconductor chip is 100 μm or less,

wherein said gettering layer is a damaged layer,

wherein the damaged layer includes a plurality of grooves,

wherein a depth of each of said grooves is 2 to 3 μm, and

wherein in plan view to said semiconductor chip, each of said grooves is a linear groove.

2. A semiconductor device comprising:

a semiconductor chip which includes an element layer formed on a front face of the semiconductor chip and a gettering layer on a back face of the semiconductor chip;

a substrate which faces the back face;

a wire; and

a resin covering the semiconductor chip, the wire and the package substrate,

wherein a thickness of said semiconductor chip is 100 μm or less,

wherein said gettering layer is a damaged layer,

wherein the damaged layer includes a plurality of grooves,

wherein a depth of each of said grooves is 2 to 3 μm, and

wherein in plan view to said semiconductor chip, each of said grooves is a linear groove, and

wherein the wire electrically connects between the substrate and the semiconductor chip.

Assignments (4)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Aug 25, 2010
From: RENESAS TECHNOLOGY CORP.
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024879/0399 →
CHANGE OF NAME Recorded Aug 25, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024879/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2005
From: MATSUKAWA, KAZUHITO; KOGA, TSUYOSHI; NISHIDA, AKIO; HIGASHIDE, YOSHIKO; SHIBATA, JUN; TOBIMATSU, HIROSHI
To: RENESAS TECHNOLOGY CORP.
Reel/Frame 016817/0754 →