IP Library Granted Patent US 7,316,941
Granted Patent B1
US 7,316,941 · App. 11/190,242 · Granted Jan 8, 2008

Semiconductor device with a MOSFET formed in close proximity to a bipolar device and method of manufacture

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Quick Facts
Patent No.
US 7,316,941
App. No.
11/190,242
Granted
Jan 8, 2008
Kind
B1
Abstract

In one embodiment, a thyristor device may be formed in series relationship with a MOSFET. Alternating regions of opposite conductivity type may be formed in semiconductor material for defining source, body and drain regions for the MOSFET device, and in series relationship to the thyristor. A primary dopant for a commonly-shared cathode/anode-emitter and drain/source region may have a concentration that is at least one order of magnitude greater than that of any background dopant therein. In a particular embodiment, the thyristor device and the MOSFET in series relationship therewith collectively define part of a thyristor-based memory.

Claims (38)

1. A method of fabricating a thyristor-based semiconductor device comprising:

forming alternating regions of opposite conductivity type in a layer of semiconductor material over an insulator and defining source, body, and drain regions for a MOSFET device and emitter and base regions for a thyristor device in series relationship;

forming the alternating regions to define one of the source and the drain regions for the MOSFET in physical common relationship with the cathode/anode-emitter region to the thyristor;

forming the drain/source region in common with the cathode/anode-emitter region by:

implanting primary dopant with dosage sufficient to establish a concentration therefore in the emitter region of at least one order of magnitude greater than that of background dopant; and

performing the implanting of the primary dopant for the emitter region to penetrate a full depth of the semiconductor material.

2. The method of claim 1 , further comprising:

determining a ratio of the primary dopant in the cathode/anode emitter region relative to background dopant sufficient to enable a gain realization for the bipolar device substantially independent of a proximity of the MOSFET; and

using a dosage and an implant energy for the implant of the primary dopant to form the emitter region with the ratio determined.

3. The method of claim 1 , further comprising:

determining a depth for the semiconductor material sufficiently thin to enable the formation of the concentration of primary dopant therethrough for the emitter region;

forming the semiconductor material over the insulator with a thickness up to the depth determined for enabling the formation of the bipolar device with a gain realization substantially independent of a proximity of the MOSFET.

4. The method of claim 3 , further comprising forming silicon for the semiconductor material over the insulator with a thickness of up to about 100 nanometers.

5. The method of claim 4 , the emitter and base regions formed for defining the thyristor in electrical series relationship with the source, body and drain regions for the MOSFET.

6. The method of claim 5 , in which the forming the silicon over the insulator comprises doping the silicon with p-type dopant; and

the forming the source and drain regions for the MOSFET and the cathode-emitter of the thyristor in common with the one of the drain/source regions comprises:

defining openings in a mask to expose regions of the layer of silicon for the source, drain and emitter regions;

using the n-type dopant as the primary dopant; and

performing the implant of the n-type dopant using a dosage of at least about 3×10 14 atoms/cm 2 and energy sufficient to penetrate the full depth of the exposed regions of the silicon layer as defined by the mask.

7. The method of claim 6 , in which the implanting uses an implant energy of at least 15 keV.

8. The method of claim 7 , further comprising:

forming a first electrode over the body region for the MOSFET; and

forming a second electrode over the base region for the thyristor; and

defining a window of the mask in part with at least one of the first and the second electrodes;

the implanting of n-type dopant for the commonly-shared drain/source and cathode-emitter region to direct the n-type dopant to exposed portions of the layer of silicon laterally between the first and second electrodes as defined by the window of the mask.

9. The method of claim 8 , in which the first and the second electrodes are formed over the layer of silicon to define a lateral distance therebetween of less than about 0.8 μm.

10. The method of claim 9 , in which the silicon layer is formed epitaxially.

11. The method of claim 10 , in which the p-type dopant for the silicon layer is diffused into the silicon for a concentration up to about 3×10 16 atoms/cm 3 .

12. The method of claim 11 , in which the forming the n-type region in the silicon layer to define the commonly-shared emitter and drain/source region comprises implanting n-type dopant with a dosage of at least about 3×10 14 atoms/cm 2 .

13. The method of claim 12 , in which the commonly-shared emitter and drain/source region is formed with a density of n-type dopant of at least about 3×10 16 atoms/cm 3 .

14. The method of claim 1 in which the implanting the primary dopant establishes a doping concentration therefore in the commonly-shared emitter and drain/source region of at least about 5×10 17 atoms/cm 3 .

15. The method of claim 14 , further comprising performing a directional halo-implant across a boundary defined between the body region and the drain/source region in the silicon layer.

16. The method of claim 15 , in which the implanting the primary dopant to define the drain/source region uses an implant energy sufficient to penetrate the full depth of the silicon with the primary dopant.

17. The method of claim 16 , in which the implanting the primary dopant uses an implant energy of at least about 15 keV.

18. The method of claim 17 , in which the forming the alternating regions of opposite conductivity type defines the cathode-emitter, p-base, n-base, and anode-emitter regions for the thyristor and the source, body, and drain regions for the MOSFET.

19. The method of claim 18 , in which the implanting the primary dopant comprises implanting n-type dopant to define the cathode-emitter region for the thyristor in common with the drain/source region for the MOSFET.

20. The method of claim 19 , in which the implanting the n-type dopant to define the cathode-emitter region in common with the drain/source region penetrates the full depth of the silicon layer with dosage sufficient to compensate residual halo implants within a portion of the cathode-emitter region proximate the insulator.

21. The method of claim 20 , in which the n-type dopant is implanted to define the cathode-emitter region penetrates the portion of the cathode-emitter region proximate the neighboring p-base region for the thyristor.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2013
From: T-RAM SEMICONDUCTOR, INC.
To: T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 031694/0018 →
PURCHASE OPTION AGREEMENT Recorded Jun 3, 2010
From: T-RAM SEMICONDUCTOR, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 024474/0979 →
RELEASE Recorded May 18, 2010
From: SILICON VALLEY BANK
To: T RAM SEMICONDUCTOR INCORPORATED
Reel/Frame 024492/0651 →
SECURITY AGREEMENT Recorded Aug 7, 2008
From: T-RAM SEMICONDUCTOR INCORPORATED
To: SILICON VALLEY BANK
Reel/Frame 021354/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2005
From: GUPTA, RAJESH
To: T-RAM SEMICONDUCTOR, INC.
Reel/Frame 016830/0639 →