Synchronous global controller for enhanced pipelining
View Patent ↗The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.
1. A controller adapted to generate different clock pulses for read and write operations in a memory block, wherein said different clock pulses are extended by said controller, and further adapted to skew at least one pre-charge signal for at least a read operation.
2. The controller of claim 1 , wherein at least one of said different clock pulses is based on a received signal.
3. The memory device of claim 1 , wherein said memory block comprises at least one memory cell.
4. The memory device of claim 1 , wherein said memory block comprises at least one local decoder.
5. The memory device of claim 1 , wherein said memory block comprises at least one local sense amp.
6. The memory device of claim 1 , wherein said memory block comprises at least one local controller.