Phase change memory cell and method of formation
View Patent ↗A phase change memory element and methods for forming the same are provided. The memory element includes a first electrode and a chalcogenide comprising phase change material layer over the first electrode. A metal-chalcogenide layer is over the phase change material layer. The metal chalcogenide layer is tin-telluride. A second electrode is over the metal-chalcogenide layer. The memory element is configured to have reduced current requirements.
1. A memory element comprising:
a first electrode;
an insulating material over the first electrode;
a via within the insulating material;
a chalcogenide comprising phase change material over the first electrode and within the via, wherein the phase change material has a thickness of less than or equal to about 100 Å at an edge of the via adjacent the first electrode;
a metal-chalcogenide material over the phase change material and within the via; and
a second electrode over the metal-chalcogenide layer.
2. The memory element of claim 1 , wherein the memory element configured to be set to a first resistance state using a current of less than or about 200 μA.
3. The memory element of claim 1 , wherein the memory element is configured to be reset to a second resistance state using a current of less than or about 280 μA.
4. The memory element of claim 1 , wherein the memory element is configured to be reset to the second resistance state using a voltage of about 1.4 V.
5. The memory element of claim 4 , wherein the memory element is configured to be set to the first resistance state using a voltage of about 1.17 V.
6. The memory element of claim 1 , wherein the phase change material comprises germanium-telluride and the metal-chalcogenide material comprises tin-telluride.
7. The memory element of claim 1 , wherein at least a portion of the phase change material has a thickness of about 300 Å.
8. The memory element of claim 1 , wherein the metal-chalcogenide material has a thickness of about 500 Å.
9. The memory element of claim 1 , wherein one or both of the first and second electrodes comprise tungsten.
10. A memory array comprising:
a plurality of memory elements, at least one memory element comprising:
a first electrode;
an insulating material over the first electrode;
a via within the insulating material;
a chalcogenide comprising phase change material over the first electrode and within the via, wherein the phase change material has a thickness of less than or equal to about 100 Å at an edge of the via adjacent the first electrode;
a metal-chalcogenide material over the phase change material and within the via, the metal chalcogenide material comprising tin-telluride; and
a second electrode over the metal-chalcogenide material.
11. The memory array of claim 10 , wherein the memory element is configured to be set to a first resistance state using a current of less than or about 200 μA.
12. The memory array of claim 11 , wherein the memory element is configured to be set to the first resistance state using a voltage of about 1.17 V.
13. The memory array of claim 10 , wherein the memory element is configured to be reset to a second resistance state using a current of less than or about 280 μA.
14. The memory array of claim 13 , wherein the memory element is configured to be reset to the first resistance state using a voltage of about 1.4 V.
15. The memory array of claim 10 , wherein at least a portion of the phase change material has a thickness of about 300 521 .
16. The memory array of claim 10 , wherein the phase change material comprises germanium-telluride.
17. The memory array of claim 10 , wherein the metal-chalcogenide material has a thickness of about 500 Å.
18. The memory array of claim 10 , wherein one or both of the first and second electrodes comprise tungsten.
19. A processor system comprising: a processor; and a memory device comprising a memory element, the memory element comprising: a first electrode; an insulating material over the first electrode; a via within the insulating material; a germanium-telluride material over the first electrode; a tin-telluride layer material over the germanium-telluride layer material, wherein the germanium-telluride material, and the tin-telluride material are within the via; and a second electrode over the tin-telluride material.
20. The system of claim 19 , wherein the germanium-telluride material has a thickness of less than or equal to about 100 Åat an edge of the via adjacent the first electrode.
21. The system of claim 19 , wherein the memory element is configured to be set to a first resistance state using a current of less than or about 200 μA.
22. The system of claim 21 , wherein the memory element is configured to be set to the first resistance state using a voltage of about 1.17 V.
23. The system of claim 19 , wherein the memory element is configured to be reset to a second resistance state using a current of less than or about 280 μA.
24. The system of claim 23 , wherein the memory element is configured to be reset to the second resistance state using a voltage of about 1.4 V.
25. The system of claim 19 , wherein at least a portion of the germanium-telluride material has a thickness of about 300 Å.
26. The system of claim 19 , wherein the tin-telluride material has a thickness of about 500 Å.
27. The system of claim 19 , wherein one or both of the first and second electrodes comprise tungsten.
28. A method for forming a memory element, the method comprising:
forming a first electrode;
forming an insulating layer over the first electrode;
forming a via within the insulating layer;
forming a chalcogenide comprising phase change material over the first electrode and within the via, wherein the phase change material layer is formed having a thickness of less than or equal to about 100 Å at an edge of the via adjacent the first electrode;
forming a metal-chalcogenide material over the phase change material and within the via; and
forming a second electrode over the metal-chalcogenide material.
29. The method of claim 28 , wherein the memory element is formed to be set to a first resistance state using a current of less than or about 200 μA.
30. The method of claim 29 , wherein the memory element is formed to be reset to a second resistance state using a current of less than or about 280 μA.
31. The method of claim 28 , wherein the memory element is formed to be reset to the second resistance state using a voltage of about 1.4 V.
32. The method of claim 31 , wherein the memory element is formed to be set to the first resistance state using a voltage of about 1.17 V.
33. The method of claim 28 , wherein at least a portion of the phase change material is formed having a thickness of about 300 Å.
34. The method of claim 28 , wherein the phase change material is formed comprising germanium-telluride and the metal-chalcogenide material is formed comprising tin-telluride.
35. The method of claim 28 , wherein the metal-chalcogenide material is formed having a thickness of about 500 Å.
36. The method of claim 28 , wherein one or both of the first and second electrodes are formed comprising tungsten.
37. A memory element comprising:
a first electrode;
an insulating material over the first electrode;
a via within the insulating material;
a germanium-telluride material within the via;
a tin-telluride layer over the germanium-telluride material and within the via; and
a second electrode over the tin-telluride material.
38. The memory element of claim 37 , wherein at least a portion of the phase change material is formed having a thickness of about 300 Å.
39. The method of claim 37 , wherein the metal-chalcogenide material is formed having a thickness of about 500 Å.