Non-volatile semiconductor memory device and semiconductor memory device
View Patent ↗For each memory block, a predecoder for predecoding an applied address signal, an address latch circuit for latching the output signal of the predecoder, and a decode circuit for decoding an output signal of the address latch circuit and performing a memory cell selecting operation in a corresponding memory block are provided. Propagation delay of latch predecode signals can be made smaller and the margin for the internal read timing can be enlarged. In addition, the internal state of the decoder and memory cell selection circuitry are rest to an initial state when a memory cell is selected and the internal data output circuitry is reset to an initial state in accordance with a state of internal data reading. Thus, a non-volatile semiconductor memory device that can decrease address skew and realize an operation with sufficient margin is provided.
1. A non-volatile semiconductor memory device, comprising:
a memory array having a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner;
predecode circuitry arranged along one side of said memory array, for predecoding an address signal designating a memory cell of said memory array, and generating a predecoded address signal;
address latch circuitry arranged along the one side of said memory array corresponding to said predecode circuitry, for latching the predecoded address signal from said predecode circuitry;
cell selecting circuitry responsive to latching of the address of said address latch circuitry, for selecting an addressed memory cell of said memory array in accordance with the latched predecoded address signal latched by said address latch circuitry; and
data reading circuitry for reading, in a data reading mode, data of the memory cell selected by said cell selecting circuitry, wherein
said memory array is divided into a plurality of blocks;
said address latch circuitry includes a plurality of address latch circuits arranged corresponding to respective blocks; and
said cell selecting circuitry includes a plurality of decode circuits, arranged corresponding to the blocks, each for decoding the address signal from the address latch circuit arranged for the corresponding block and generating a cell selection signal, with interconnections between said plurality of address latch circuits and corresponding decode circuits being made equal in length to each other.
2. The non-volatile semiconductor memory device according to claim 1 , wherein
said predecode circuitry includes a plurality of predecode circuits arranged corresponding to the blocks, and an output signal of each of said predecode circuits is applied to a corresponding address latch circuit.
3. A non-volatile semiconductor memory device, comprising:
a memory array having a plurality of non-volatile memory cells, arranged in rows and columns, each for storing data in a non-volatile manner;
predecode circuitry arranged along one side of said memory array, for predecoding an address signal designating a memory cell of said memory array, and generating a predecoded address signal;
address latch circuitry arranged along the one side of said memory array corresponding to said predecode circuitry, for latching the predecoded address signal from said predecode circuitry;
cell selecting circuitry responsive to latching of the address of said address latch circuitry, for selecting an addressed memory cell of said memory array in accordance with the latched predecoded address signal latched by said address latch circuitry; and
data reading circuitry for reading, in a data reading mode, data of the memory cell selected by said cell selecting circuitry, wherein
said cell selecting circuitry resets said address latch circuitry to an initial state, after a memory cell is selected.
4. The non-volatile semiconductor memory device according to claim 3 , wherein
said cell selecting circuitry further resets an internal state of said cell selecting circuitry to an initial state, after said memory cell is selected.
5. The non-volatile semiconductor memory device according to claim 4 , wherein
said data reading circuitry includes a sense amplifier circuit for amplifying data of said selected memory cell to generate an internal read data; and
said cell selecting circuitry resets said address latch circuitry in response to a signal controlling activation of said sense amplifier circuit.