Testing method for LCD panels
The present invention provides a testing method for LCD panels. First, a plurality of panels are formed on a substrate. Each panel has first conducting lines and second conducting lines, which are perpendicular to each other. The first conducting lines and the second conducting lines of adjacent panels are electrically connected, respectively. Finally, all panels on the substrate are simultaneously tested by a testing circuit.
1. A testing method for liquid crystal display panels, the testing method comprising:
forming a plurality of panels on a substrate, wherein the panels respectively include plural first conducting lines and plural second conducting lines, which are perpendicular to each other;
forming plural third conducting lines between the adjacent panels to directly connect the first conducting lines or the second conducting lines of the adjacent panels in a straight direction; and
testing the panels simultaneously.
2. The testing method for liquid crystal display panels of claim 1 , wherein the first conducting lines are plural source lines.
3. The testing method for liquid crystal display panels of claim 1 , wherein the second conducting lines are plural gate lines.
4. The testing method for liquid crystal display panels of claim 1 , wherein the substrate is a glass substrate.
5. The testing method for liquid crystal display panels of claim 1 , wherein the testing step is performed by a testing circuit.
6. The testing method for liquid crystal display panels of claim 5 , wherein the size of the testing circuit is the same as the total area of the panels.
7. The testing method for liquid crystal display panels of claim 5 , wherein the testing circuit comprises plural testing pins.
8. The testing method for liquid crystal display panels of claim 7 , wherein the testing pins electrically connect to plural source pads of the source lines and to plural gate pads of the gate lines in the testing step.
9. The testing method for liquid crystal display panels of claim 1 , wherein the sizes of the panels are the same.
10. The testing method for liquid crystal display panels of claim 1 , wherein the panels comprise at least two different sizes.
11. A layout for testing liquid crystal display panels on a substrate simultaneously, the layout comprising:
panels located on the substrate, the panels including first conducting lines and second conducting lines, wherein the second conducting lines are perpendicular to the first conducting lines; and
third conducting lines, which are located between the adjacent panels to directly connect the first conducting lines or the second conducting lines of the adjacent panels in a straight direction.
12. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the first conducting lines are plural source lines.
13. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the second conducting lines are plural gate lines.
14. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the substrate is a glass substrate.
15. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the sizes of the panels are the same.
16. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the panels comprise at least two different sizes.
17. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 11 , wherein the testing step is performed by a testing circuit.
18. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 17 , wherein the size of the testing circuit is the same as the total area of the panels.
19. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 17 , wherein the testing circuit comprises plural testing pins.
20. The layout for testing liquid crystal display panels on a substrate simultaneously of claim 19 , wherein the testing pins electrically connect to plural source pads of the source lines and to plural gate pads of the gate lines in the testing step.