Read access and storage circuitry read allocation applicable to a cache
View Patent ↗A read allocation indicator (e.g. read allocation signal 30 ) is provided to storage circuitry (e.g. cache 22 ) to selectively determine whether read allocation will be performed for the read access. Read allocation may include modification of the information content of the cache ( 22 ) and/or modification of the read replacement algorithm state implemented by the read allocation circuitry ( 70 ) in cache ( 22 ). For certain types of debug operations, it may be very useful to provide a read allocation indicator that ensures that no unwanted modification are made to the storage circuitry during a read access. Yet other types of debug operations may want the storage circuitry to be modified in the standard manner when a read access occurs.
1. A method for performing a debug operation, comprising:
initiating the debug operation requiring a read access to a cache and having a debug operation type; and
selectively performing read allocation during the debug operation, based at least on the debug operation type.
2. The method of claim 1 , wherein read allocation comprises at least one of modifying contents of the cache and modifying a read allocation state of the cache.
3. The method of claim 2 , wherein when the debug operation type is a first type, read allocation is performed during the read access and when the debug operation type is a second type, read allocation is not performed during the read access.
4. The method of claim 2 , wherein when the debug operation type is a first type, a read allocation indicator corresponding to the read access is provided to the cache to indicate that read allocation is to be performed for the read access, and when the debug operation is a second type, a read allocation indicator corresponding to the read access is provided to the cache to indicate that no read allocation is to be performed for the read access.
5. An apparatus, comprising:
a cache;
interconnect circuitry coupled to the cache; and
debug circuitry, coupled to the interconnect circuitry, the debug circuitry initiating a debug operation requiring a read access to the cache and providing, during the debug operation, a read allocation indicator to the cache corresponding to the read access via the interconnect circuitry.
6. The apparatus of claim 5 , wherein the cache, in response to the read allocation indicator, selectively performs read allocation during the read access.
7. The apparatus of claim 6 , wherein the cache, in response to the read allocation indicator and based on the debug operation, selectively performs read allocation during the read access.
8. The apparatus of claim 5 , wherein when the read allocation indicator has a first value, the read access is performed with read allocation and when the read allocation indicator has a second value, the read access is performed without read allocation.
9. The apparatus of claim 5 , wherein the interconnect circuitry comprises switching circuitry to route the read allocation indicator from the debug circuitry to the cache.
10. The apparatus of claim 5 , wherein the interconnect circuitry comprises a system bus coupled to the debug circuitry and to the cache, and wherein the read allocation indicator is provided via the system bus.