Low-power low-voltage multi-level variable-resistor line driver

1. A line driver circuit including a first output terminal and a second output terminal, the line driver circuit to transmit data through the first output terminal and the second output terminal, the line driver circuit comprising:

a first pull-up variable resistor and a first switch connected in series between a first power supply and the first output terminal, the first power supply being at a fixed regulated voltage;

a second pull-up variable resistor and a second switch connected in series between the first power supply and the second output terminal;

a first pull-down variable resistor and a third switch connected in series between a second power supply and the first output terminal;

a second pull-down variable resistor and a fourth switch connected in series between the second power supply and the second output terminal;

a floating variable resistor connected between the first output terminal and the second output terminal; and

a coder logic to receive data bits and adjust an output voltage across the first output terminal and the second output terminal by varying resistances of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor to modulate an amplitude of the output voltage across the first output terminal and the second output terminal at the fixed regulated voltage of the first power supply and responsive to the received data bits,

wherein an effective parallel resistance value of the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, the second pull-down variable resistor, and the floating variable resistor coupled together is fixed to maintain an effective output impedance for the line driver circuit that equals an impedance of a transmission line connected to the first output terminal and the second output terminal.

2. The line driver circuit of claim 1 , wherein the coder logic is further operable to set the resistance of the first pull-up variable resistor and the second pull-up variable resistor to a value that is different from the resistance of the first pull-down variable resistor and the second pull-down variable resistor to generate a controlled common-mode voltage associated with an adjustable output voltage.

3. The line driver circuit of claim 1 , further comprising a voltage regulator to regulate a voltage of the first power supply to twice a maximum signal swing of the adjustable output voltage.

4. The line driver circuit of claim 3 , wherein the adjustable output voltage is adjustable from zero to the maximum signal swing.

5. The line driver circuit of claim 4 , wherein power consumption of the line driver circuit is directly proportional to the adjustable output voltage.

6. The line driver circuit of claim 5 , wherein a drive current associated with the line driver circuit is directly proportional to the adjustable output voltage.

7. The line driver circuit of claim 1 , wherein the coder logic is operable to digitally set the resistance of each of the floating variable resistor, the first pull-up variable resistor, the second pull-up variable resistor, the first pull-down variable resistor, and the second pull-down variable resistor to modulate the amplitude of the output voltage.

8. The line driver circuit of claim 1 , wherein the line driver circuit is a multi-level pulse amplitude modulation (PAM) line driver circuit having more than two voltage levels.

9. The line driver of claim 8 , wherein the multi-level pulse amplitude modulation (PAM) line driver circuit is compliant with 100Base-T or 1000Base-T protocols.

10. The line driver circuit of claim 1 , wherein the amplitude modulation provided by the coder logic provides more than two voltage levels.

11. The line driver circuit of claim 1 , wherein the coder modulates the amplitude of the output voltage by setting different resistance values for each of first and second pairs of variable resistors at the same time to adjust the amplitude of the output voltage, the first pair including one of the first and second pull-up variable resistors and one of the first and second pull-down variable resistors, and the second pair including a different one of the first and second pull-up variable resistors and a different one of the first and second pull-down variable resistors.