IP Library Granted Patent US 8,208,540
Granted Patent B2
US 8,208,540 · App. 11/198,457 · Granted Jun 26, 2012

Video bitstream transcoding method and apparatus

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,208,540
App. No.
11/198,457
Granted
Jun 26, 2012
Kind
B2
Abstract

A video transcoder is disclosed. The video transcoder generally comprises a processor and a video digital signal processor. The processor may be formed on a first die. The video digital signal processor may be formed on a second die and coupled to the processor. The video digital signal processor may have (i) a first module configured to perform a first operation in decoding an input video stream in a first format and (ii) a second module configured to perform a second operation in coding an output video stream in a second format, wherein the first operation and the second operation are performed in parallel.

Claims (31)

1. A video transcoder comprising:

a processor configured to (i) generate a plurality of commands and (ii) perform part of at least one of a decoding and a coding; and a video digital signal processor coupled to said processor, said video digital signal processor having (i) a first module configured to generate a first intermediate signal and a second intermediate signal by performing a first operation in said decoding of an input video stream in response to said commands, wherein said input video stream is in a first format, (ii) a memory configured to buffer said first intermediate signal and (iii) a second module configured to perform a second operation in said coding of said first intermediate signal based on decoding information in said second intermediate signal to generate an output video stream, wherein (a) said output video stream is in a second format, (b) said second format is different than said first format, (c) said first intermediate signal conveys a sequence of decoded images, (d) said decoding information in said second intermediate signal is extracted from said input video stream during said decoding, and (e) said first module configured to transfer partially decoded images to said second module before said first module has completed decoding of an entire image, so that said second module operates in parallel with said first module, wherein said first operation and said second operation are performed simultaneously.

2. The video transcoder according to claim 1 , wherein said first operation comprises an inverse quantization in said decoding of said input video stream and said second operation comprises a quantization in said coding to generate said output video stream.

3. The video transcoder according to claim 1 , wherein said first operation comprises an inverse transform in said decoding of said input video stream and said second operation comprises a forward transform in said coding to generate said output video stream.

4. The video transcoder according to claim 1 , wherein said first operation comprises a decompression of a first motion vector in said decoding of said input video stream and said second operation comprises a compression of a second motion vector in said coding to generate said output video stream.

5. The video transcoder according to claim 1 , wherein said memory is configured to (i) buffer pixel information written from said first module and (ii) read said pixel information directly to said second module.

6. The video transcoder according to claim 1 , wherein said first operation comprises a first motion compensation in said decoding of said input video stream and said second operation comprises a second motion compensation in said coding to generate said output video stream.

7. The video transcoder according to claim 6 , wherein said second motion compensation uses a motion vector decoded from said input video stream by said first module as a center of a search in a reference image.

8. The video transcoder according to claim 1 , wherein said first module is further configured to perform a third operation in said coding to generate said output video stream.

9. The video transcoder according to claim 8 , wherein (i) said first operation is a first motion compensation in said decoding of said input video stream, (ii) said third operation is a second motion compensation in said coding to generate said output video stream and (iii) said second motion compensation is performed serially after said first motion compensation.

10. The video transcoder according to claim 1 , wherein said first operation comprises variable length decoding of said input video stream and said second operation comprises variable length coding to generate said output video stream.

11. A method for video transcoding comprising the steps of:

(A) generating a plurality of commands in a processor;

(B) performing part of at least one of a decoding and a coding in said processor; and

(C) generating a first intermediate signal and a second intermediate signal in a video digital signal processor by performing a first operation in said decoding of an input video stream in response to said commands, wherein said input video stream is in a first format,

(D) buffering said first intermediate signal in a memory; and

(E) performing a second operation in said coding of said first intermediate signal based on decoding information in said second intermediate signal to generate an output video stream, wherein (i) said output video stream is in a second format, (ii) said second format is different than said first format, (iii) said first intermediate signal conveys a sequence of decoded images, (iv) said decoding information in said second intermediate signal is extracted from said input video stream during said decoding, and (v) said first module configured to transfer partially decoded images to said second module before said first module has completed decoding of an entire image, so that said second module operates in parallel with said first module, wherein said first operation and said second operation are performed simultaneously.

12. The method according to claim 11 , wherein said first operation comprises an inverse quantization in said decoding of said input video stream and said second operation comprises a quantization in said coding to generate said output video stream.

13. The method according to claim 11 , wherein said first operation comprises an inverse transform in said decoding of said input video stream and said second operation comprises a forward transform in said coding to generate said output video stream.

14. The method according to claim 11 , wherein said first operation comprises a decompression of a first motion vector in said decoding of said input video stream and said second operation comprises a compression of a second motion vector in said coding to generate said output video stream.

15. The method according to claim 11 , further comprising the steps of:

buffering in a memory pixel information written from said first operation; and

reading said pixel information directly from said memory to said second operation.

16. The method according to claim 11 , wherein said first operation comprises a first motion compensation in said decoding of said input video stream and said second operation comprises a second motion compensation in said coding to generate said output video stream.

17. The video transcoder according to claim 16 , wherein said second motion compensation uses a motion vector decoded from said input video stream by said first operation as a center of a search in a reference image.

18. The method according to claim 11 , wherein said first operation comprises a first motion compensation performed by a module in said decoding of said input video stream, the method further comprising the step of:

performing a second motion compensation in said coding to generate said output video stream in said module, wherein said second motion compensation is performed serially after said first motion compensation.

19. The method according to claim 11 , wherein said first operation comprises variable length decoding of said input video stream and said second operation comprises variable length coding to generate said output video stream.

20. A video transcoder comprising:

means for processing configured to (i) generate a plurality of commands and (ii) perform part of at least one of a decoding and a coding; and

means for video digital signal processing coupled to said means for processing, said means for video digital signal processing having (i) a first module configured to generate a first intermediate signal and a second intermediate signal by performing a first operation in said decoding of an input video stream in response to said commands, wherein said input video stream is in a first format, (ii) a memory configured to buffer said first intermediate signal and (iii) a second module configured to perform a second operation in said coding of said first intermediate signal based on data in said second intermediate signal to generate an output video stream, wherein (a) said output video stream is in a second format, (b) said second format is different than said first format, (c) said first intermediate signal conveys a sequence of decoded images, (d) said decoding information in said second intermediate signal is extracted from said input video stream during said decoding, and (e) said first module configured to transfer partially decoded images to said second module before said first module has completed decoding of an entire image, so that said second module operates in parallel with said first module, wherein said first operation and said second operation are performed simultaneously.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded May 15, 2012
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 028209/0377 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2005
From: COTE, GUY
To: LSI LOGIC CORPORATION
Reel/Frame 016867/0556 →
Continuity (1)
Related Publication 20070030905A1 · Feb 8, 2007