Logic device with reduced leakage current
A logic device operates with reduced leakage current. Controllability is achieved by using a reference voltage to control the amount of leakage reduction. A method of temperature dependent reference voltage generation is given which maintains virtual supply in acceptable range to provide sufficient noise margin in logic devices including memory cells.
1. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcing/sinking current to/from said logic devices; and
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals, said voltage controlled constriction devices being biased by reference voltages between less than a supply voltage and more than a ground voltage to reduce the leakage current in an area efficient manner.
2. The logic device with reduced leakage current as in claim 1 wherein said logic device includes circuitry selected from the group consisting of memory cells, SRAM based content addressable memory, and bitline precharge circuitry.
3. The logic device with reduced leakage current as in claim 1 wherein said constriction devices are biased from the reference voltages whose levels are variably controlled.
4. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcing/sinking current to/from said logic devices; and
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals, said voltage controlled constriction devices being biased to reduce the leakage current in an area efficient manner;
wherein said constriction devices are biased from diodes/diode connected transistors connected between said supply terminals and gates of said constriction devices, and a temperature tracking mechanism connected between said diodes/diode connected transistors.
5. The logic device with reduced leakage current as in claim 4 wherein said temperature-tracking mechanism includes a reference logic cell array.
6. The logic device with reduced leakage current as in claim 1 wherein said constriction devices comprise:
a small-sized PMOS transistor connected between said supply terminals and said virtual supply terminals of said logic devices;
a small-sized NMOS transistor connected between said supply terminals and said virtual supply terminals of said logic devices;
thereby providing constriction in the path of supply to said logic devices.
7. The logic device with reduced leakage current as in claim 1 wherein a decoupling capacitance is provided with said supply terminals of said logic devices to provide stable supply/sink in normal operation.
8. A logic device with reduced leakage current, comprising:
an array of logic devices;
a switch connected between each supply terminal and each virtual supply terminal of said logic devices for sourcing/sinking current to said logic devices;
voltage controlled constriction devices connected between said supply terminals and said virtual supply terminals;
said voltage controlled constriction devices being biased from:
diodes/diode connected transistors connected between said supply terminals and gates of said constriction devices; and
a temperature tracking mechanism connected between said diodes/diode connected transistors, to thereby reducing the leakage current in an area efficient manner.
9. An integrated circuit, comprising:
logic circuitry coupled to a virtual ground; and
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor source/drain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal having a voltage between but not equal to either a supply reference and the ground reference that changes an amount of current sourced by the first transistor.
10. The integrated circuit of claim 9 wherein the logic circuitry is coupled between the virtual ground and a virtual supply, further comprising a decoupling capacitance defining the virtual supply and virtual ground.
11. An integrated circuit, comprising:
logic circuitry coupled to a virtual ground;
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor source/drain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal that changes an amount of current sourced by the first transistor; and
a tracking circuit comprised of same logic circuitry and operable to track leakage current of that same logic circuitry and generate the first control signal to change the amount of current sourced by the first transistor so as to maintain a substantially steady voltage across the logic circuitry.
12. The integrated circuit of claim 9 wherein the logic circuitry is coupled between the virtual ground and a virtual supply, further comprising a supply constriction circuit coupled between the virtual supply and a supply reference, the supply constriction circuit including a second transistor source/drain coupled between the virtual supply and supply reference and having a gate terminal coupled to receive a second control signal that changes an amount of current sourced by the second transistor.
13. An integrated circuit, comprising:
logic circuitry coupled between a virtual ground and a virtual supply;
a ground constriction circuit coupled between the virtual ground and a ground reference, the ground constriction circuit including a first transistor source/drain coupled between the virtual ground and ground reference and having a gate terminal coupled to receive a first control signal that changes an amount of current sourced by the first transistor;
a supply constriction circuit coupled between the virtual supply and a supply reference, the supply constriction circuit including a second transistor source/drain coupled between the virtual supply and supply reference and having a gate terminal coupled to receive a second control signal that changes an amount of current sourced by the second transistor; and
a tracking circuit comprised of same logic circuitry and operable to track leakage current of that same logic circuitry and generate the first and second control signals to change the amount of current sourced by the first and second transistors so as to maintain a substantially steady voltage across the logic circuitry.