Copper line of semiconductor device and method for forming the same
View Patent ↗A copper line on a semiconductor device and a method for forming the same is disclosed, wherein an insulating layer is deposited so as to minimize the dishing of IMD without using a dummy area when performing the planarization process. The method of forming the copper line on the semiconductor device includes the steps of forming an IMD on a semiconductor substrate including a lower metal layer, forming an isolation layer on the IMD, exposing the lower metal layer by patterning the IMD and the isolation layer, forming a copper layer on the exposed lower metal layer and the isolation layer, and planarizing the copper layer.
1. A method for forming a copper line of a semiconductor device comprising:
forming a lower metal layer on a semiconductor substrate;
forming an IMD over said semiconductor substrate and over said lower metal layer;
forming a single isolation layer on the IMD;
exposing the lower metal layer by patterning the IMD and the isolation layer;
forming a copper layer on the exposed lower metal layer and the isolation layer, the copper layer being in direct contact with the lower metal layer; and
planarizing the copper layer while using the isolation layer to prevent dishing on the IMD.
2. The method of claim 1 , wherein the isolation layer is formed of silicon nitride.
3. The method of claim 1 , wherein the isolation layer is formed of a thickness of 500 Å to 1500 Å.
4. A copper line of a semiconductor device comprising:
a lower metal layer on a semiconductor substrate;
an IMD over said semiconductor substrate and over said lower metal layer;
an isolation layer on the IMD; and
a copper line through the IMD and the isolation layer, the copper line being in direct contact with the lower metal layer,
wherein the copper line is formed by CMP and no dishing on the IMD results from the CMP process.