Programmable embedded logic analyzer in an integrated circuit
View Patent ↗A logic analyzer having internal access to the test buses, clocks and events of a chip is used to debug the chip. The logic analyzer is designed with the capability to share existing memory in the chip during the debug process. Additionally, the configuration of the logic analyzer and observation of the acquired results in the shared memory can be accessed through normal control interfaces of the chip and does not require special test cards. The logic analyzer includes a clocking function, a trigger function, a signal multiplexer, and a memory block. The clocking function is configured to select as the sample clock for the function any of the clocks in the integrated circuit. In addition, the clocking function may provide a means to decimate these clocks by some factor to sample over larger intervals.
1. A method for sampling internal data signals of an integrated circuit having a communication port, a plurality of buses, and an embedded logic analyzer coupled to both the communication port and the plurality of buses, comprising:
(1) programming the embedded logic analyzer through the communication port, wherein the programming comprises selecting one of the integrated circuit's internal clocks for use as a sampling-clock;
(2) sampling data signals from one of the plurality of buses using the embedded logic analyzer, wherein the sampling comprises decimating the sample clock by an integer n; and
(3) storing the sampled data signals.
2. The method of claim 1 , wherein step (1) comprises:
selecting one of the plurality of buses for data sampling; and
setting trigger conditions for the embedded logic analyzer to control the step of data sampling on the selected bus.
3. The method of claim 2 , wherein step (2) comprises: collecting data signals from the selected bus in response to the sampling-clock; and
identifying the trigger conditions on the selected bus.
4. The method of claim 3 , wherein step (2) comprises:
synchronizing the collected data with the identified trigger conditions.
5. The method of claim 1 , wherein step (3) comprises:
storing the, collected data signals along with corresponding trigger events data into a memory.
6. The method of claim 5 , wherein the memory is in the integrated circuit.
7. The method of claim 5 , wherein the memory is a RAM.
8. The method of claim 5 , wherein the memory is shared with the integrated circuit.
9. The method of claim 1 , wherein the communication port is a joint test action group port.
10. The method of claim 1 , wherein the integrated circuit is a transceiver circuit.
11. The method of claim 1 , wherein step (1) comprises:
setting trigger conditions for the embedded logic analyzer to control the data sampling process.
12. An integrated circuit, comprising:
a communication port;
a plurality of buses; and
a programmable logic analyzer circuit coupled to both the communication port and the plurality of buses, wherein
the programmable logic analyzer circuit is programmed through the communication ports,
the programmable logic analyzer circuit samples data signals from a selected one of the plurality of buses,
the programmable logic analyzer circuit includes a clock selector that selects an internal clock of the integrated circuit for use as a sampling-clock, and
the programmable logic analyzer circuit includes a clock decimator for decimating the sampling-clock by an integer n.
13. The integrated circuit of claim 12 , wherein the programmable logic analyzer circuit comprises:
a clock delay for delaying the sampling-clock;
a signal selector that selects a first plurality of buses for data capturing;
a data capture register that stores data signals from the first plurality of buses in response to the sampling-clock;
a trigger source selector that selects a second plurality of buses for data monitoring;
trigger control logic that detects trigger conditions by monitoring data signals from the second plurality of buses; and
a control state machine, wherein the control state machine causes signal data from the data capture register and state data from the control state machine to be stored into a memory in response to the trigger control logic.
14. The integrated circuit of claim 13 , wherein the programmable logic analyzer circuit further comprises:
a synchronizer for synchronizing data from the data capture register with the detected trigger conditions.
15. The integrated circuit of claim 13 , wherein the memory is shared with the microprocessor.
16. The integrated circuit of claim 13 , wherein the memory is a dedicated memory that is used exclusively by the programmable logic analyzer circuit.
17. The integrated circuit of claim 13 , wherein the first and second plurality of buses are different.
18. The integrated circuit of claim 12 , wherein the communication port is a joint test action group port.
19. The integrated circuit of claim 12 , wherein the microprocessor is coupled to a transceiver circuit.
20. An integrated circuit, comprising:
a communication port;
a plurality of buses; and
a programmable logic analyzer coupled to both the communication port and the plurality of buses, the programmable logic analyzer can be programmed through the communication port to sample data signals from a selected plurality of buses, the programmable logic analyzer comprising:
a clock generator;
a clock selector that selects either an internal clock of the integrated circuit or the clock generator for use as a sampling-clock;
a clock delay for delaying the sampling-clock;
a clock decimator for decimating the sampling-clock by n, wherein n is an integer;
a signal selector that selects a first plurality of buses for data capturing;
a data capture register that stores data signals from the first plurality of buses in response to the sampling-clock;
a trigger source selector that selects a second plurality of buses for data monitoring;
trigger control logic that detects trigger conditions by monitoring data signals from the second plurality of buses; and
a control state machine, wherein the state machine causes signal data from the data capture register and state data from the state machine to be stored into a memory in response to the trigger control logic.
21. The integrated circuit of claim 20 , wherein the first and second plurality of buses are different.