Semiconductor devices to reduce stress on a metal interconnect
View Patent ↗Semiconductor devices to reduce stress on a metal interconnect are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.
1. A semiconductor device comprising:
a semiconductor substrate;
an uppermost metal interconnect formed on the semiconductor substrate;
an oxide layer formed on the uppermost metal interconnect, wherein the oxide layer is on the entire top surface of the uppermost metal interconnect;
an aluminum layer formed on the oxide layer; and
a stress-relief layer formed on the aluminum layer.
2. A semiconductor device as defined in claim 1 , wherein the stress-relief layer comprises an aluminum oxide layer.
3. A semiconductor device as defined in claim 1 , wherein the aluminum layer is formed in a thickness of 100 to 300 Å.
4. A semiconductor device as defined in claim 1 , wherein the oxide layer is formed of one of an undoped silica glass and a fluorinated silica glass.
5. A semiconductor device as defined in claim 1 , wherein the semiconductor device is at least one of a multi-interconnect adapted device and a power device.