Semiconductor device and method for fabricating the same
View Patent ↗When a via-hole 26 and an interconnection trench 32 are formed in an interconnection films 16, 18 by using as a mask a hard mask 20 covering the region except via-hole forming region, and a hard mask 22 covering the region except an interconnection trench forming region, the hard mask 20 is isotropically etched to expose the upper surface of the inter-layer insulating film 18 at a periphery of the via-hole forming region and leave the hard mask 20 in the interconnection trench forming region except the periphery, and then the hard mask 20 and the insulating films 18, 16 are anisotropically etched, whereby the via-hole 26 having increased-width portion 34 at the upper part, and the interconnection trench 32 connected to the via-hole 26 at the increased-width portions 26 are formed.
1. A method for fabricating a semiconductor device comprising the steps of:
sequentially forming over a substrate an insulating film, a first mask, and a second mask whose etching characteristics are different from those of the first mask;
forming on the second mask a photoresist film exposing a via-hole forming region;
anisotropically etching the second mask and the first mask in the via-hole forming region with the photoresist film as a mask;
anisotropically etching the insulating film in the via-hole forming region down to the middle thereof with the photoresist film, the second mask and the first mask as a mask;
removing the second mask in an interconnection trench forming region containing the via-hole forming region;
isotropically etching the first mask with the second mask as a mask to expose an upper surface of the insulating film at a peripheral region of the via-hole forming region and to leave the first mask in the interconnection trench forming region except the peripheral region;
anisotropically etching the first mask and the insulating film with the second mask as a mask to form in the insulating film a via-hole having an increased-width portion at an upper part and an interconnection trench connected to the increased-width portion of the via-hole; and
filling an interconnection in the via-hole and the interconnection trench.
2. A method for fabricating a semiconductor device according to claim 1 , wherein
the step of forming the via-hole and the interconnection trench includes the steps of:
anisotropically etching the first mask under conditions which make an etching selectively with respect to the insulating film small to thereby etch the first mask on the insulating film and selectively etch the insulating film at the peripheral region to form the increased-width portions; and
anisotropically etching the insulating film to deepen the via-hole down to the substrate and to form the interconnection trench.
3. A method for fabricating a semiconductor device comprising the steps of:
sequentially forming over a substrate an insulating film, a first mask, and a second mask whose etching characteristics are different from those of the first mask;
forming on the second mask a photoresist film exposing an via-hole forming region;
anisotropically etching the second mask in the via-hole forming region with the photoresist film as a mask;
removing the photoresist film;
anisotropically etching the first mask in the via-hole forming region with the second mask as a mask;
anisotropically etching the insulating film in the via-hole forming region down to the middle thereof with the second mask as a mask;
removing the second mask in an interconnection trench forming region containing the via-hole forming region;
isotropically etching the first mask with the second mask as a mask to expose an upper surface of the insulating film in a peripheral region of the via-hole forming region and to leave the first mask in the interconnection trench forming region except the peripheral region;
anisotropically etching the first mask and the insulating film with the second mask as a mask to form in the insulating film a via-hole having an increased-width portion at an upper part and an interconnection trench connected to the increased-width portion of the via-hole; and
filling an interconnection in the via-hole and the interconnection trench.
4. A method for fabricating a semiconductor device according claim 1 , which further comprises the steps of:
forming on the second mask a third mask whose etching characteristics are different from those of the second mask; and
removing the third mask in the interconnection trench forming region, and in which
in the step of removing the second mask in the interconnection trench forming region, the second mask is anisotropically etched with the third mask as a mask.
5. A method for fabricating a semiconductor device according to claim 1 , wherein
a configuration of the increased-width portion of the via-hole is controlled by controlling an etching amount of the first mask in the step of isotropically etching the first mask.
6. A method for fabricating a semiconductor device comprising the steps of:
sequentially forming over a substrate an insulating film, a first mask, a second mask whose etching characteristics are different from those of the first mask, and a third mask whose etching characteristics are different from those of the second mask;
removing the first mask, the second mask and the third mask in a via-hole forming region;
anisotropically etching the insulating film in the via hole forming region to the middle thereof;
removing the third mask in the interconnection trench forming region containing the via-hole forming region;
isotropically etching the second mask with the third mask as a mask to expose an upper surface of the first mask at a peripheral region of the via-hole forming region and to leave the second mask in the interconnection trench forming region except the peripheral region;
anisotropically etching the second mask, the first mask and the insulating film with the third mask as a mask to form in the insulating film a via-hole having an increased-width portion at an upper part, and an interconnection trench connected to the increased-width portion of the via-hole; and
filling an interconnection in the via-hole and the interconnection trench.
7. A method for fabricating a semiconductor device according to claim 6 , wherein
the step of forming the via-hole and the interconnection trench includes the steps of:
anisotropically etching the second mask under conditions which make an etching selectivity with respect to the first mask small to etch the second mask on the first mask and selectively etch the first mask at the peripheral region;
anisotropically etching the first mask under conditions which make an etching selectivity with respect to the insulating film small to etch the first mask on the insulating film and etch the insulating film selectively at the peripheral region to form the increased-width portion; and
further anisotropically etch the insulating film to deepen the via-hole down to the substrate and form the interconnection trench.
8. A method for fabricating a semiconductor device according to claim 6 , wherein
the step of removing the third mask, the second mask and the first mask formed in the via-hole forming region includes the steps of:
forming on the third mask a photoresist film exposing the via-hole forming region; and
anisotropically etching the third mask, the second mask and the first mask with the photoresist film as a mask, and
in the step of anisotropically etching the insulating film in the via-hole forming region, the insulating film is etched with the photoresist film, the third mask, the second mask and the first mask as a mask.
9. A method for fabricating a semiconductor device according to claim 6 , wherein
the step of removing the third mask, the second mask and the first mask in the via-hole forming region includes the steps of:
forming on the third mask a photoresist film exposing the via-hole forming region;
anisotropically etching the third mask and the second mask in the via-hole forming region with the photoresist film as the mask;
removing the photoresist film; and
anisotropically etching the first mask in the via-hole forming region with the third mask and the second mask as a mask.
10. A method for fabricating a semiconductor device according to claim 6 , wherein
a configuration of the increased-width portion of the via-hole is controlled by controlling an etching amount of the second mask in the step of isotropically etching the second mask.
11. A method for fabricating a semiconductor device according claim 3 , which further comprises the steps of:
forming on the second mask a third mask whose etching characteristics are different from those of the second mask; and
removing the third mask in the interconnection trench forming region, and in which
in the step of removing the second mask in the interconnection trench forming region, the second mask is anisotropically etched with the third mask as a mask.
12. A method for fabricating a semiconductor device according to claim 3 , wherein
a configuration of the increased-width portion of the via-hole is controlled by controlling an etching amount of the first mask in the step of isotropically etching the first mask.