Semiconductor device
View Patent ↗The semiconductor device according to the present invention comprises an output MOS transistor M 0 , an MOS transistor M 3 connected between a gate G 1 of the output MOS transistor M 0 and a ground voltage GND, a parasitic transistor Tr 1 which is formed in parallel with the MOS transistor M 3 with the substrate terminal of the MOS transistor M 3 as a base, and a parasitic transistor control circuit for controlling the conducting status of the parasitic transistor Tr 1 based on the power supply voltage Vcc.
1. A semiconductor device, comprising:
an output transistor connected between a first power supply terminal and an output terminal, and passing an output current in accordance with a signal applied to a current control terminal thereof;
an over current protection element connected between the current control terminal and a second power supply terminal;
a first detection circuit applied with a voltage through the first power supply terminal, detecting a current flowing through the output transistor to provide a detection signal to a first control terminal of the over current protection element; and
a second detection circuit applied with a voltage through the first power supply terminal, detecting a current flowing through the output transistor to provide a detection signal to a second control terminal of the over current protection element, and operating at a voltage lower than the first detection circuit.
2. The semiconductor device according to claim 1 , wherein the over current protection element is a first MOS transistor including a gate connected to the first control terminal and a substrate connected to the second control terminal.
3. The semiconductor device according to claim 2 , wherein:
the second detection circuit includes a resistance element and a second MOS transistor connected in series between the first power supply terminal and the second power supply terminal; and
a series-connection node between the resistance element and the second MOS transistor is connected to the substrate of the first MOS transistor.
4. The semiconductor device according to claim 2 , wherein the first detection circuit includes a control circuit connected between the first power supply terminal and the second power supply terminal, and an output terminal of the control circuit is connected to the gate of the first MOS transistor.
5. The semiconductor device according to claim 3 , wherein the first detection circuit includes a control circuit connected between the first power supply terminal and the second power supply terminal, and an output terminal of the control circuit is connected to the gate of the first MOS transistor.
6. The semiconductor device according to claim 1 , wherein when an over current flows through the output transistor due to the output terminal short-circuited to the second power supply terminal, the second detection circuit provides a detection signal to the over current protection to act so as to discharge accumulated charges at the current control terminal and shift the output transistor to a non-operation state, and the first detection circuit starts to operate due to an increase in potential of the first power supply terminal resulting from the shift to the non-operation state to bring the output transistor completely into a non-operation state.
7. The semiconductor device according to claim 2 , wherein when an over current flows through the output transistor due to the output terminal short-circuited to the second power supply terminal, the second detection circuit outputs a detection signal to the over current protection to act so as to discharge accumulated charges at the current control terminal and shift the output transistor to a non-operation state, and the first detection circuit starts to operate due to an increase in potential of the first power supply terminal resulting from the shift to the non-operation state to bring the output transistor completely into a non-operation state.
8. The semiconductor device according to claim 3 , wherein when an over current flows through the output transistor due to the output terminal short-circuited to the second power supply terminal, the second detection circuit outputs a detection signal to the over current protection to act so as to discharge accumulated charges at the current control terminal and shift the output transistor to a non-operation state, and the first detection circuit starts to operate due to an increase in potential of the first power supply terminal resulting from the shift to the non-operation state to bring the output transistor completely into a non-operation state.
9. The semiconductor device according to claim 3 , wherein the resistance element is a depletion-type MOS transistor.
10. The semiconductor device according to claim 3 , further comprising a constant voltage source provided between the first power supply terminal and a gate of the second MOS transistor.
11. The semiconductor device according to claim 3 , further comprising a third MOS transistor connected to a gate of the second MOS transistor and having substantially the same structure as the second MOS transistor.
12. The semiconductor device according to claim 1 , further comprising a diode inserted between the current control terminal and the over current protection element and preventing backflow of a current.
13. The semiconductor device according to claim 3 , wherein a plurality of wells are located on a main surface of a semiconductor substrate in an isolated form, and the first MOS transistor and the second MOS transistor are located in different wells.
14. The semiconductor device according to claim 1 , wherein the over current protection element is connected to the second power supply terminal through the output terminal.
15. The semiconductor device according to claim 1 , wherein the output transistor is an N-channel type MOS transistor.
16. The semiconductor device according to claim 1 , wherein an external load is connected between the output terminal and the second power supply terminal, and the first power supply terminal has a potential higher than a potential of the second power supply terminal.