Ferroelectric memory
A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.
1. A ferroelectric memory comprising:
a base member;
a first dielectric layer formed above the base member;
a second dielectric layer formed above the first dielectric layer;
a contact hole that penetrates the first dielectric layer and the second dielectric layer;
a first barrier layer formed in the contact hole, an upper edge of the first barrier layer being lower than a surface of the second dielectric layer;
a plug formed in the contact hole,
wherein an upper edge of the plug is lower than the upper edge of the first barrier layer;
a second barrier layer formed above the first barrier layer and the plug; and
a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug,
wherein the second dielectric layer has a property that is more difficult to polish than the plug and the first dielectric layer.
2. A ferroelectric memory according to claim 1 , further comprising an adhesion layer formed between the lower electrode and the second barrier layer and formed in a region including the lower electrode.
3. A ferroelectric memory according to claim 1 , wherein the second barrier layer includes one of a titanium aluminum nitride layer and a titanium nitride layer.
4. A ferroelectric memory according to claim 1 , wherein the second dielectric layer includes one of a silicon nitride layer, a silicon oxinitride layer and an aluminum oxide layer.
5. A ferroelectric memory according to claim 1 , wherein the plug is formed inside the first barrier layer.
6. A ferroelectric memory according to claim 1 , wherein an upper surface of the second barrier layer has a same surface height as the second dielectric layer.