Non-volatile semiconductor memory device and method for reading the same
View Patent ↗In a reference cell 202 , first and second cells 50 and 52 having the same structure as that of a memory cell are provided. A memory cell current IREF 1 of the first cell 50 is set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREF 2 of the second cell 52 is set to be a maximum value of a memory cell current after a write operation. The read circuit 206 compares a memory cell current Icell with a current (IREF 1 +IREF 2 )/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cells 50 and 52.
1. A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells, from the memory cell set in one of at least two states, the method comprising the steps of:
obtaining a read current of the memory cell to be read as a first current;
obtaining a second current based on a first verification reference current used for erase verification of the memory cell and a second verification reference current used for write verification of the memory cell; and
calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
2. The method according to claim 1 , wherein
the step of obtaining the second current includes obtaining a sum current of the first verification reference current and the second verification reference current as the second current, and
the step of calculating the data includes comparing the first current with a half of the second current.
3. The method according to claim 1 , wherein
the step of obtaining the second current includes obtaining a sum current of the first verification reference current and the second verification reference current as the second current, and
the step of calculating the data includes comparing a double of the first current with the second current.
4. A circuit for reading data from a non-volatile semiconductor memory device comprising a plurality of memory cells, the circuit comprising:
a first current generation circuit of generating a first verification reference current used for erase verification of the memory cell;
a second current generation circuit of generating a second verification reference current used for write verification of the memory cell;
a first current supply circuit of supplying a read current as a first current to the memory cell to be read;
a second current supply circuit of supplying a second current based on the first verification reference current and the second verification reference current; and
a comparison section of calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
5. The circuit according to claim 4 , wherein
the second current supply circuit supplies a sum current of the first verification reference current and the second verification reference current as the second current, and
the comparison section comprises:
a third current supply circuit of supplying a third current corresponding to the first current;
a fourth current supply circuit of supplying a fourth current corresponding to the second current; and
a comparison circuit of comparing the third current with the fourth current.
6. The read circuit according to claim 5 , wherein
the third current has the same amount as that of the first current, and the fourth current is a half of the second current.
7. The read circuit according to claim 5 , wherein
the third current is a double of the first current, and the fourth current has the same amount as that of the second current.
8. A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell set in one of at least two states, wherein
a first reference cell is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state, and
a second reference cell is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state,
the method comprising the steps of:
obtaining a read current of the memory cell to be read as a first current;
obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell; and
calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
9. The method according to claim 8 , wherein
the step of obtaining the second current includes obtaining a sum current of the read current of the first reference cell and the read current of the second reference cell as the second current, and
the step of calculating the data includes comparing the first current with a half of the second current.
10. The method according to claim 8 , wherein
the step of obtaining the second current includes obtaining a sum current of the read current of the first reference cell and the read current of the second reference cell as the second current, and
the step of calculating the data includes comparing a double of the first current with the second current.
11. A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell set in one of at least three states, wherein
a first one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state,
a second one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state, and
the remaining reference cell or cells are set so that a read current thereof coincides with a predetermined value,
the method comprising the steps of:
obtaining a read current of the memory cell to be read as a first current;
obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell;
obtaining a third current based on read currents of two of the reference cells other than the first reference cell;
calculating a first comparison result, depending on whether the first current is larger than, smaller than, or equal to the second current;
calculating a second comparison result, depending on whether the first current is larger than, smaller than, or equal to the third current; and
calculating data stored in the memory cell to be read based on the first comparison result and the second comparison result.
12. The method according to claim 11 , wherein
the non-volatile semiconductor memory device comprises at least four reference cells,
a third one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in the second state,
a fourth one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a third state,
the step of obtaining the second current includes obtaining a sum current of the read current of the first reference cell and the read current of the second reference cell as the second current, and
the step of obtaining the third current includes obtaining a sum current of the read current of the third reference cell and the read current of the fourth reference cell as the third current.
13. The method according to claim 11 , wherein
the non-volatile semiconductor memory device comprises at least four reference cells,
a third one of the reference cells is set so that a read current thereof coincides with a representative value of a read current of the memory cell set in the second state,
a fourth one of the reference cells is set so that a read current thereof coincides with a representative value of a read current of the memory cell set in a third state,
the step of obtaining the second current includes obtaining a sum current of the read current of the first reference cell and the read current of the second reference cell as the second current, and
the step of obtaining the third current includes obtaining a sum current of the read current of the third reference cell and the read current of the fourth reference cell as the third current.
14. The method according to claim 11 , wherein
the non-volatile semiconductor memory device comprises at least three reference cells,
a third one of the reference cells is set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a third state,
the step of obtaining the second current includes obtaining a sum current of the read current of the first reference cell and the read current of the second reference cell as the second current, and
the step of obtaining the third current includes obtaining a sum current of the read current of the second reference cell and the read current of the third reference cell as the third current.
15. The method according to claim 11 , wherein
the step of calculating the first comparison result includes comparing the first current with a half of the second current, and
the step of calculating the second comparison result includes comparing the first current with a half of the third current.
16. The method according to claim 11 , wherein
the step of calculating the first comparison result includes comparing a double of the first current with the second current, and
the step of calculating the second comparison result includes comparing a double of the first current with the third current.
17. A circuit for reading data from a non-volatile semiconductor memory device comprising a plurality of memory cells, the circuit comprising:
a first reference cell set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a first state;
a second reference cell set so that a read current thereof coincides with a maximum or minimum value of a read current of the memory cell set in a second state;
a first current supply circuit of supplying a read current as a first current to the memory cell to be read;
a second current supply circuit of supplying a second current based on the read current of the first reference cell and the read current of the second reference cell; and
a comparison section of calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second current.
18. The circuit according to claim 17 , wherein
the second current supply circuit supplies, as the second current, a sum current of the read current of the first reference cell and the read current of the second reference cell, and
the comparison section comprises:
a third current supply circuit of supplying a third current corresponding to the first current;
a fourth current supply circuit of supplying a fourth current corresponding to the second current; and
a comparison circuit of comparing the third current with the fourth current.
19. The circuit according to claim 18 , wherein
the third current has the same amount as that of the first current, and the fourth current is a half of the second current.
20. The circuit according to claim 18 , wherein
the third current is a double of the first current, and the fourth current has the same amount as that of the second current.
21. A method for reading data, in a non-volatile semiconductor memory device comprising a plurality of memory cells and a plurality of reference cells, from the memory cell, wherein
the memory cells are divided into a first type such that the memory cell is set to be one of at least four states on a block-by-block basis, and a second type such that the memory cell is set to be one of at least two states,
each memory cell block is associated with at least four reference cells,
the first to fourth reference cells of the first type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in one of the four states,
the first and third reference cells of the second type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in one of the two states, and
the second and fourth reference cells of the second type memory cell are set so that respective read currents coincide with a maximum or minimum value of a read current of a memory cell set in the other of the two states,
the method comprising the steps of:
obtaining a read current of the memory cell to be read as a first current;
obtaining a second current based on the read current of the first reference cell and the read current of the second reference cell;
obtaining a third current based on the read current of the second reference cell and the read current of the third reference cell;
obtaining a fourth current based on the read current of the third reference cell and the read current of the fourth reference cell; and
calculating data stored in the memory cell to be read, depending on whether the first current is larger than, smaller than, or equal to the second to fourth currents.