IP Library Granted Patent US 8,502,082
Granted Patent B2
US 8,502,082 · App. 11/215,206 · Granted Aug 6, 2013

Circuitized substrate utilizing three smooth-sided conductive layers as part thereof and electrical assemblies and information handling systems utilizing same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,502,082
App. No.
11/215,206
Granted
Aug 6, 2013
Kind
B2
Abstract

A circuitized substrate in which three conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to two dielectric layers. Each of the foil surfaces which physically bond to a respective dielectric layer are smooth (e.g., preferably by chemical processing) and may include a thin, organic layer thereon. One of the conductive layers may function as a ground or voltage (power) plane while the other two may function as signal planes with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.

Claims (27)

1. A circuitized substrate comprising:

a first electrically conductive layer with first and second opposing major surfaces, both of said surfaces having an RMS roughness value less than approximately 0.6 micron;

a thin organic layer disposed on said first and second opposing major surfaces;

first and second dielectric layers directly bonded to said first and second opposing major surfaces, respectively;

second and third electrically conductive layers each having a first smooth side directly bonded to said first and second dielectric layers, respectively, said second and third electrically conductive layers each further including a second opposing side, all of said second and third layer first and second sides having an RMS roughness value less than approximately 0.6 micron; and

a circuit pattern formed within at least one of said second and third electrically conductive layers having said first smooth surface and said second surface, whereby said substrate is formed with a polymer alternative.

2. The circuitized substrate of claim 1 wherein said first, second and third electrically conductive layers each comprises copper or copper alloy material.

3. The circuitized substrate of claim 2 wherein said copper or copper alloy material is electrodeposited copper.

4. The circuitized substrate of claim 1 further including a thin organic layer on said first and second sides of said first electrically conductive layer and said sides of said second and third electrically conductive layers, said thin organic layer comprising benzotriazole and having a thickness of from about 50 Angstroms to about 500 Angstroms.

5. The circuitized substrate of claim 1 further including additional dielectric and electrically conductive layers on opposite sides of said circuitized substrate having said first and second dielectric layers and said first, second and third electrically conductive layers, and a circuit pattern within selected ones of said additional electrically conductive layers.

6. The circuitized substrate of claim 5 wherein the total number of dielectric layers and electrically conductive layers within said circuitized substrate is greater than ten.

7. An electrical assembly comprising:

a circuitized substrate including a first electrically conductive layer with first and second opposing major surfaces, a thin organic layer disposed on first and second dielectric layers directly bonded to said first and second opposing major surfaces, respectively, second and third electrically conductive layers each having a first surface directly bonded to said first and second dielectric layers, respectively, said second and third electrically conductive layers each further including a respective second opposing surface, all of said surfaces having an RMS roughness value of less than approximately 0.6 micron, a circuit pattern formed within at least one of said second and third electrically conductive layers; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

8. The electrical assembly of claim 7 wherein said at least one electrical component comprises a semiconductor chip and said circuitized substrate is a chip carrier substrate.

9. The electrical assembly of claim 7 further including a thin organic layer on said first and second sides of said first electrically conductive layer and said sides of said second and third electrically conductive layers, said thin organic layer comprising benzotriazole and having a thickness of from about 50 Angstroms to about 500 Angstroms.

10. The electrical assembly of claim 7 wherein said first, second and third electrically conductive layers comprises copper or copper alloy material.

11. The electrical assembly of claim 10 wherein said copper or copper alloy material is electrodeposited copper.

12. The electrical assembly of claim 7 further including additional dielectric and electrically conductive layers on opposite sides of said circuitized substrate, said first and second dielectric layers, and said first, second and third electrically conductive layers, and a circuit pattern within selected ones of said additional electrically conductive layers.

13. The electrical assembly of claim 12 wherein the total number of dielectric layers and electrically conductive layers within said circuitized substrate is greater than ten.

14. An information handling system comprising:

a housing;

a circuitized substrate disposed in said housing and including a first electrically conductive layer with first and second opposing major surfaces, a thin organic layer disposed on first and second dielectric layers directly bonded to said first and second opposing major surfaces, respectively, second and third electrically conductive layers each having a first surface directly bonded to said first and second dielectric layers, respectively, said second and third electrically conductive layers each further including a respective second opposing surface, all of said surfaces having an RMS value less than approximately 0.6 micron, a circuit pattern formed within at least one of said second and third electrically conductive layers; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

15. The invention of claim 14 wherein said information handling system comprises a personal computer.

16. The invention of claim 14 wherein said information handling system comprises a mainframe computer.

17. The invention of claim 14 wherein said information handling system comprises a computer server.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →