Patent Assignment
Reel/Frame 035098/0968
Release of Security Interest
Recorded: 2015-02-26
Pages: 22
Assignee
ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
1093 CLARK STREET, ENDICOTT, NEW YORK, 13760
Covered Properties
(168)
Circuitized Substrate Assembly and Method of Making Same
Circuitized Substrate and Method of Making Same
Information Handling System Utilizing Circuitized Substrate
Multi-Chip Electronic Package Having Laminate Carrier and Method of Making Same
Information Handling System
Material Separation to Form Segmented Product
Electronic Package with Strengthened Conductive Pad
Pinned Electronic Package with Strengthened Conductive Pad
Method of testing spacings in pattern of openings in PCB conductive layer
Electronic Component Test Apparatus
Circuitized Substrate and Method of Making Same
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Method of Making Circuitized Substrate
Method of making multilayered printed circuit board with filled conductive holes
Printed Circuit Board with Low Cross-Talk Noise
Item Identification Control Method
Circuitized Substrate with Signal Wire Shielding, Electrical Assembly Utilizing Same and Method of Making
Method of Making High Speed Circuit Board
Method of Making Circuitized Substrate Assembly
Dielectric Composition for Forming Dielectric Layer for Use in Circuitized Substrates
Circuitized Substrate
Method and System for Tracking Goods
Radio Frequency Device for Tracking Goods
Circuitized Substrate with Split Conductive Layer, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Circuitized Substrate with Filled Isolation Border, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Circuitized Substrate with Internal Organic Memory Device, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Electrical Assembly with Internal Memory Circuitized Substrate Having Electronic Components Positioned Thereon, Method of Making Same, and Information Handling System Utilizing Same
Circuitized Substrate Assembly and Method of Making Same
Low Moisture Absorptive Circuitized Substrate, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Information Handling System Utilizing Circuitized Substrate
Circuitized Substrate with Improved Impedance Contol Circuitry, Method of Making Same, Electrical Assembly and Information Handling System Utilizing Same
High Speed Circuitized Substrate with Reduced Thru-Hole Stub, Method for Fabrication and Information Handling System Utilizing Same
Method of Making a Circuitized Substrate Having a Plurality of Solder Connection Sites Thereon
Circuitized Substrates Utilizing Three Smooth-Sided Conductive Layers as Part Thereof, Method of Making Same, and Electrical Assemblies and Information Handling Systems Utilizing Same
Patent:
6,964,884 →
Application:
10/991,451 →
Method of Making Circuitized Substrates Utilizing Smooth-Sided Conductive Layers as Part Thereof
Capacitor Material with Metal Component for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate
Patent:
7,025,607 →
Application:
11/031,074 →
Capacitor Material for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate
Low Moisture Absorptive Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Electronic Card Assembly
Interposer for Use with Test Apparatus
Apparatus and Method for Making Circuitized Substrates in a Continuous Manner
Apparatus for Making Circuitized Substrates Having Photo-Imageable Dielectric Layers in a Continuous Manner
Multi-Chip Electronic Package with Reduced Line Skew and Circuitized Substrate for Use Therein
Plating Method for Circuitized Substrates
Wirebond Electronic Package with Enhanced Chip Pad Design, Method of Making Same, and Information Handling System Utilizing Same
Resistor Material with Metal Component for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Ciruitized Substrate, and Information Handling System Utilizing Said Ciruitized Substrate
Method of Making an Internal Capacitive Substrate for Use in a Circuitized Substrate and Method of Making Said Circuitized Substrate
Method of Making Multilayered Circuitized Substrate Assembly Having Sintered Paste Connections
Circuitized Substrate with Sintered Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same
Circuitized Substrate Utilizing Three Smooth-Sided Conductive Layers as Part Thereof and Electrical Assemblies and Information Handling Systems Utilizing Same
Method and Apparatus for Depositing Conductive Paste in Circuitized Substrate Openings
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Circuitized Substrate with Conductive Polymer and Seed Material Adhesion Layer
Circuitized Substrate with Soler-Coated Microparticle Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same and Method of Making Said Substrate
Method of Making Circuitized Substrate
Method of Making Circuitized Substrate
Dielectric Composition for Use in Circuitized Substrates and Circuitized Substrate Including Same
Substrate Test Apparatus and Method of Testing Substrates
Patent:
7,129,732 →
Application:
11/281,456 →
Method of Improving Electrical Connections in Circuitized Substrates
Capacitor material with metal component for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate
Application:
11/324,273 →
Publication:
US 2006/0154501
Method of Making Circuitized Substrate
Method of Treating Conductive Layer for Use in a Circuitized Substrate and Method of Making Said Substrate Having Said Conductive Layer as Part Thereof
Method of making printed circuit board having varying depth conductive holes
Application:
11/334,445 →
Publication:
US 2006/0121722
Method of Making Circuitized Substrate
Method of Making Circuitized Substrate Assembly
Information Handling System Including a Circuitized Substrate Having a Dielectric Layer Without Continuous Fibers
Method of Making a Capacitive Substrate Using Photoimageable Dielectric for Use as Part of a Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making an Information Handling System Including Said Circuitized Substrate
Method of Making a Capacitive Substrate for Use as Part of a Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making an Information Handling System Including Said Circuitized Substrate
Fluoropolymer Dielectric Composition for Use in Circuitized Substrates and Circuitized Substrate Including Same
Adjustable Thickness Thermal Interposer and Electronic Package Utilizing Same
Method of Providing Printed Circuit Board with Conductive Holes and Board Resulting Therefrom
Circuitized Substrate with Shielded Signal Lines and Plated-Thru-Holes and Method of Making Same, and Electrical Assembly and Information Handling System Utilizing Same
Method of Making Circuitized Substrate with Signal Wire Shielding
Capacitive Substrate
High Speed Interposer
Method of Making a Multi-Chip Electronic Package Having Laminate Carrier
Method of Making Circuitized Substrate with Filled Isolation Border
Photoresist Composition with Antibacterial Agent
Circuitized Substrate Assembly
Halogen-Free Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Multilayered Substrate Structure Utilizing Same, and Information Handling System Utilizing
Method of Making a Circuitized Substrate with Enhanced Circuitry and Electrical Assembly Utilizing Said Substrate
Method of Making Circuitized Substrate with Solder Paste Connections
Interposer and Test Assembly for Testing Electronic Devices
Method of Making a Printed Circuit Board with Low Cross-Talk Noise
Method of Making Circuitized Substrate with Split Conductive Layer and Information Handling System Utilizing Same
Method of making circuitized substrate with solder balls having roughened surfaces, method of making electrical assembly including said circuitized substrate, and method of making multiple circuitized substrate assembly
Application:
11/650,520 →
Publication:
US 2008/0164300
Method of Providing a Printed Circuit Board with an Edge Connection Portion and/or a Plurality of Cavities Therein
Flexible Circuit Electronic Package with Standoffs
Method of Making Circuitized Substrate with Selected Conductors Having Solder Thereon
Led Lighting Assembly and Lamp Utilizing Same
Non-flaking capacitor material, capacitive substrate having an internal capacitor therein including said non-flaking capacitor material, and method of making a capacitor member for use in a capacitive substrate
Application:
11/730,761 →
Publication:
US 2007/0177331
Method of Making Same Low Moisture Absorptive Circuitized Substrave with Reduced Thermal Expansion
Circuitized Substrate with Internal Stacked Semiconductor Chips, Method of Making Same, Electrical Assembly Utilizing Same and Information Handling System Utilizing Same
Method for Making a Multilayered Circuitized Substrate
Method of Making Circuitized Substrate with a Resistor
Circuitized Substrate with Conductive Paste, Electrical Assembly Including Said Circuitized Substrate and Method of Making Said Substrate
Circuitized Substrate with Internal Resistor, Method of Making Said Circuitized Substrate, and Electrical Assembly Utilizing Said Circuitized Substrate
Method of Providing a Printed Circuit Board with an Edge Connection Portion
Method of Making Circuitized Substrate with Internal Organic Memory Device
Method of Making Wirebond Electronic Package with Enhanced Chip Pad Design
Adhesive bleed prevention method and product produced from same
Application:
11/882,149 →
Publication:
US 2009/0035455
Apparatus for Making Circuitized Substrates in a Continuous Manner
Method of Making Circuitized Substrate with Improved Impedance Control Circuitry, Electrical Assembly and Information Handling System
Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers
Method of Making an Interposer
Method of Making Multilayered Circuitized Substrate Assembly
Method of Making Circuitized Substrate with Internal Optical Pathway Using Photolithography
Method of Making Circuitized Substrate with Internal Optical Pathway
Circuitized Substrate with Internal Cooling Structure and Electrical Assembly Utilizing Same
Circuitized substrate with increased roughness conductive layer as part thereof
Application:
11/976,629 →
Publication:
US 2008/0054476
Method of Making Multi-Chip Electronic Package with Reduced Line Skew
Circuitized substrate with sintered paste connections and multilayered substrate assembly having said substrate as part thereof
Application:
12/007,178 →
Publication:
US 2008/0105457
Method of making circuitized assembly including a plurality of circuitized substrates
Application:
12/007,704 →
Publication:
US 2009/0178273
Method of Making Circuitized Substrates Having Film Resistors as Part Thereof
Information Handling System Utilizing Circuitized Substrate with Split Conductive Layer
High Speed Interposer
Circuitized, multilayer substrate
Application:
12/078,206 →
Publication:
US 2009/0241332
Multilayered Circuitized Substrate with P-Aramid Dielectric Layers and Method of Making Same
Circuitized Substrate with Continuous Thermoplastic Support Film Dielectric Layers
Circuitized Substrates Utilizing Smooth-Sided Conductive Layers as Part Thereof
Spring Actuated Clamping Mechanism
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Capacitive Substrate and Method of Making Same
Multilayered Circuitized Substrate with P-Aramid Dielectric Layers and Method of Making Same
Method of Making Halogen-Free Circuitized Substrate with Reduced Thermal Expansion
Method of making a circuitized substrate with continuous thermoplastic support film dielectric layers
Application:
12/380,637 →
Publication:
US 2009/0258161
Photosensitive dielectric film
Application:
12/460,975 →
Publication:
US 2011/0017498
Method of making a circuitized substrate
Electronic Package Including High Density Interposer and Circuitized Substrate Assembly Utilizing Same
Method of Making High Density Interposer and Electronic Package Utilizing Same
Method for Making Circuitized Substrates Having Photo-Imageable Dielectric Layers in a Continuous Manner
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Coreless Layer Buildup Structure
Coreless Layer Buildup Structure with Lga
Coreless Layer Buildup Structure with Lga and Joining Layer
Method for via Plating in Electronic Packages Containing Fluoropolymer Dielectric Layers
Application:
12/765,110 →
Publication:
US 2011/0260299
Power Core for Use in Circuitized Substrate and Method of Making Same
High Density Connector for Interconnecting Fine Pitch Circuit Packaging Structures
Semi-Conductor Chip with Compressible Contact Structure and Electronic Package Utilizing Same
Method of Forming Fibrous Laminate Chip Carrier Structures
Application:
12/837,584 →
Publication:
US 2012/0012553
A Method of Joining a Semiconductor Device/Chip to a Printed Wiring Board
Circuitized Substrates Utilizing Smooth-Sided Conductive Layers as Part Thereof
Liquid Crystal Polymer Layer for Encapsulation and Improved Hermiticity of Circuitized Substrates
Anti-Tamper Microchip Package Based on Thermal Nanofluids or Fluids
Conducting Paste for Device Level Interconnects
Land Grid Array (Lga) Contact Connector Modification
Application:
12/904,305 →
Publication:
US 2012/0243147
Method of Forming Multilayer Capacitors in a Printed Circuit Substrate
Electronic Package and Method of Making Same
Application:
12/910,020 →
Publication:
US 2012/0162928
Method of Making Circuitized Substrate with Resistor Including Material with Metal Component and Electrical Assembly and Information Handling System Utilizing Said Circuitized Substrate
High Bandwidth Semiconductor Ball Grid Array Package
Application:
12/939,659 →
Publication:
US 2012/0112345
Circuitized Substrate with Dielectric Interposer Assembly and Method
Conductive Metal Nub for Enhanced Electrical Interconnection, and Information Handling System Utilizing Same
Application:
13/009,922 →
Publication:
US 2012/0243155
Electronic Package with Thermal Interposer and Method of Making Same
Defective Conductive Surface Pad Repair for Microelectronic Circuit Cards
Application:
13/041,655 →
Publication:
US 2012/0228013
Circuitized Substrate with Internal Thin Film Capacitor and Method of Making Same
Application:
13/042,578 →
Publication:
US 2012/0228014
Method of Cavity Forming on a Buried Resistor Layer Using a Fusion Bonding Process
Conductive Metal Micro-Pillars for Enhanced Electrical Interconnection
Application:
13/082,502 →
Publication:
US 2012/0257343
Modular, Detachable Compute Leaf for Use with Computing System
Application:
13/082,599 →
Publication:
US 2012/0260063
Method of Applying Force to Electrical Contacts on a Printed Circuit Board
A Method of Forming an Electrically Conductive Printed Line
Patent:
8,499,445 →
Application:
13/184,699 →
Thermal Substrate
Application:
13/189,980 →
Publication:
US 2013/0025839
Liquid Crystal Polymer (Lcp) Surface Layer Adhesion Enhancement
Application:
13/197,804 →
Publication:
US 2013/0033671
Electrically Conductive Adhesive (Eca) for Multilayer Device Interconnects
Method of Making a Circuitized Substrate
Circuitized Substrate with Low Loss Capacitive Material and Method of Making Same
Patent:
8,446,707 →
Application:
13/269,770 →
Solder and Electrically Conductive Adhesive Based Interconnection for Czt Crystal Attach
Patent:
8,592,299 →
Application:
13/358,716 →
Method of Making a Semiconductor Radiation Detector
Substrate Having Internal Capacitor and Method of Making Same
Patent:
8,607,445 →
Application:
13/517,776 →
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Release by Secured Party
May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
Security Agreement
May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
Assignment of Assignor's Interest
Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
Security Interest
Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
Assignment of Assignor's Interest
Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
Assignment of Assignor's Interest
Nov 4, 2020
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 054269/0366 →
Patent Security Agreement (Abl)
May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
Patent Security Agreement (Term Loan)
May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
Release of Security Interest in Patents Previously Recorded at Reel/Frame (063804/0702)
Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →