Method of making an internal capacitive substrate for use in a circuitized substrate and method of making said circuitized substrate
View Patent ↗A method of forming a capacitive substrate in which first and second conductors are formed opposite a dielectric, with one of these electrically coupled to a thru-hole connection. Each functions as an electrode for the resulting capacitor. The substrate is then adapted for being incorporated within a larger structure to form a circuitized substrate such as a printed circuit board or a chip carrier. Additional capacitors are also possible.
1. A method of making a capacitive substrate, said method comprising:
providing a conductive layer;
providing a capacitive dielectric layer comprised of a mixture of a polymer material and a ferroelectric ceramic crystalline nanoparticle material, said capacitive dielectric layer having a thickness of from about 0.1 mils to about 5 mils and including first and second opposing sides;
bonding said first opposing side of said capacitive dielectric layer to said conductive layer;
curing said capacitive dielectric layer on said conductive layer at a temperature from about 150 degrees Celsius to about 200 degrees Celsius;
forming at least one first conductor on said second opposing side of said capacitive dielectric layer after said curing of said capacitive dielectric layer;
forming an electrical connection through said capacitive dielectric layer to said at least one first conductor; and
forming at least one second conductor from said conductive layer, said at least one second conductor not being electrically connected to said at least one first conductor and said electrical connection through said capacitive dielectric layer, each of said at least one first and second conductors serving as capacitor electrodes when said conductors are electrically coupled to other circuit structure and said circuit structure is operational.
2. The method of claim 1 wherein said bonding of said capacitive dielectric layer to said conductive layer is accomplished using a process selected from the group of processes consisting of screen printing, ink-jet printing and coating.
3. The method of claim 2 wherein said curing of said material of said capacitive dielectric layer is accomplished in a time period of from about 100 minutes to about 140 minutes.
4. The method of claim 1 wherein said forming of said electrical connection through said capacitive dielectric layer comprises forming a hole within said capacitive dielectric layer and thereafter depositing electrically conductive material within said hole.
5. The method of claim 4 wherein said forming of said hole is accomplished by a drilling operation using a mechanical drill or a laser.
6. The method of claim 5 wherein said depositing of said electrically conductive material within said hole is accomplished using a plating operation.
7. The method of claim 1 wherein said forming of said at least one second conductor from said conductive layer is accomplished using photolithographic processing.
8. A method of making a capacitive substrate having first and second capacitors therein, said method comprising:
providing first and second conductive layers;
providing first and second capacitive dielectric layers each comprised of a mixture of a polymer material and a ferroelectric ceramic crystalline nanoparticle material, said first and second capacitive dielectric layers each having a thickness of from about 0.1 mils to about 5 mils and including first and second opposing sides;
bonding said first opposing side of said first capacitive dielectric layer to said first conductive layer and said first opposing side of said second capacitive dielectric layer to said second conductive layer;
curing said first and second capacitive dielectric layers on said first and second conductive layers respectively at a temperature from about 150 degrees Celsius to about 200 degrees Celsius;
forming at least one first conductor on each of said second opposing sides of said first and second capacitive dielectric layers, respectively after said curing of said first and second capacitive dielectric layers;
forming an electrical connection through each of said first and second capacitive dielectric layers to said at least one first conductor on each of said second opposing sides of said first and second capacitive dielectric layers, respectively; and
forming at least one second conductor from each of said first and second conductive layers, respectively, each of said at least one second conductors not being electrically connected to the corresponding one of said at least one first conductors and said electrical connections through said capacitive dielectric layers, each of said at least one first and second conductors on said first and second capacitive dielectric layers serving as capacitor electrodes for a single capacitor when said conductors are electrically coupled to other circuit structure and said circuit structure is operational.
9. The method of claim 8 wherein said bonding of said capacitive dielectric layer to said conductive layer is accomplished using a process selected from the group of processes consisting of screen printing, ink-jet printing and coating, the material of said capacitive dielectric layer being substantially cured, said curing of said material of said capacitive dielectric layers being accomplished in a time period of from about 100 minutes to about 140 minutes.
10. The method of claim 8 wherein said forming of said electrical connections through said capacitive dielectric layers comprises forming a hole within each of said capacitive dielectric layers and thereafter depositing electrically conductive material within said holes.
11. The method of claim 10 wherein said forming of said holes is accomplished by a drilling operation using a mechanical drill or a laser.
12. The method of claim 11 wherein said depositing of said electrically conductive material within said holes is accomplished using a plating operation.
13. The method of claim 1 wherein said forming of said at least one second conductor from said conductive layers is accomplished using photolithographic processing.
14. A method of making a circuitized substrate having a capacitive substrate therein, said method comprising:
providing a conductive layer;
providing a capacitive dielectric layer comprised of a mixture of a polymer material and a ferroelectric ceramic crystalline nanoparticle material, said capacitive dielectric layer having a thickness of from about 0.1 mils to about 5 mils and including first and second opposing sides;
bonding said first opposing side of said capacitive dielectric layer to said conductive layer;
curing said capacitive dielectric layer on said conductive layer at a temperature from about 150 degrees Celsius to about 200 degrees Celsius;
forming at least one first conductor on said second opposing side of said capacitive dielectric layer after said curing of said capacitive dielectric layer;
forming an electrical connection through said capacitive dielectric layer to said at least one first conductor;
forming at least one second conductor from said conductive layer, said at least one second conductor not being electrically connected to said at least one first conductor and said electrical connection through said capacitive dielectric layer;
forming a dielectric layer on said capacitive dielectric layer over said at least one second conductor and said electrical connection;
forming third and fourth conductors on said dielectric layer; and
electrically coupling said third conductor to said at least one first conductor and said fourth conductor to said electrical connection to form an electrical circuit including said, at least one first and second conductors, said third and fourth conductors and said electrical connection, each of said at least one first and second conductors serving as capacitor electrodes of a capacitor within said electrical circuit when said electrical circuit is operational.
15. The method of claim 14 wherein said forming of said dielectric layer on said capacitive dielectric layer over said at least one second conductor and said electrical connection is accomplished using a lamination procedure.
16. The method of claim 14 wherein said forming of said third and fourth conductors on said dielectric layer is accomplished using photolithographic processing.
17. A method of making a circuitized substrate having a capacitive substrate therein including first and second capacitors, said method comprising:
providing first and second conductive layers;
providing first and second capacitive dielectric layers each comprised of a mixture of a polymer material and a ferroelectric ceramic crystalline nanoparticle material, said first and second capacitive dielectric layers each having a thickness of from about 0.1 mils to about 5 mils and including first and second opposing sides;
bonding said first opposing side of said first capacitive dielectric layer to said first conductive layer and said first opposing side of said second capacitive dielectric layer to said second conductive layer;
curing said first and second capacitive dielectric layers on said first and second conductive layers respectively at a temperature from about 150 degrees Celsius to about 200 degrees Celsius;
forming at least one first conductor on each of said second opposing sides of said first and second capacitive dielectric layers, respectively after said curing of said first and second capacitive dielectric layers;
forming first and second electrical connections through said first and second capacitive dielectric layers, respectively, to said at least one first conductor on each of said second opposing sides of said first and second capacitive dielectric layers, respectively;
forming at least one second conductor from each of said first and second conductive layers, respectively, each of said at least one second conductors not being electrically connected to the corresponding one of said at least one first conductors and said electrical connections through said capacitive dielectric layers;
forming a dielectric layer on each of said capacitive dielectric layers over each of said at least one second conductors and said electrical connections, respectively;
forming third and fourth conductors on one of said dielectric layers, and fifth and sixth conductors on a second of said dielectric layers, respectively;
electrically coupling said third conductor to one of said at least one first conductors and said fourth conductor to said first electrical connection to form a first electrical circuit including said at least one first and second conductors, said third and fourth conductors and said first electrical connection, each of said at least one first and second conductors serving as capacitor electrodes of a first capacitor within said electrical circuit when said first electrical circuit is operational; and
electrically coupling said fifth conductor to one of said at least one first conductors and said sixth conductor to said second electrical connection to form a second electrical circuit including said at least one first and second conductors, said fifth and sixth conductors and said second electrical connection, each of said at least one first and second conductors serving as capacitor electrodes of a second capacitor within said second electrical circuit when said second electrical circuit is operational.
18. The method of claim 17 wherein said forming of said dielectric layers on each of said capacitive dielectric layers over said at least one second conductor and said electrical connection is accomplished using a lamination procedure.
19. The method of claim 18 wherein said forming of said third and fourth conductors on one of said dielectric layers and said forming of said fifth and sixth conductors on the second of said dielectric layers is accomplished using photolithographic processing.