Patent Assignment
Reel/Frame 040608/0626
Security Interest
Recorded: 2016-11-14
Pages: 20
Assignor
I3 ELECTRONICS, INC.
Executed: 2016-11-03
Assignee
M&T BANK
ONE M&T PLAZA, ATTN: OFFICE OF GENERAL COUNSEL, BUFFALO, NEW YORK, 14203
Covered Properties
(94)
Circuitized Substrate Assembly and Method of Making Same
Circuitized Substrate and Method of Making Same
Information Handling System Utilizing Circuitized Substrate
Material Separation to Form Segmented Product
Electronic Package with Strengthened Conductive Pad
Pinned Electronic Package with Strengthened Conductive Pad
Method of testing spacings in pattern of openings in PCB conductive layer
Electronic Component Test Apparatus
Circuitized Substrate and Method of Making Same
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Method of making multilayered printed circuit board with filled conductive holes
Printed Circuit Board with Low Cross-Talk Noise
Circuitized Substrate with Signal Wire Shielding, Electrical Assembly Utilizing Same and Method of Making
Dielectric Composition for Forming Dielectric Layer for Use in Circuitized Substrates
Circuitized Substrate
Method and System for Tracking Goods
Circuitized Substrate with Split Conductive Layer, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Circuitized Substrate with Filled Isolation Border, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Electrical Assembly with Internal Memory Circuitized Substrate Having Electronic Components Positioned Thereon, Method of Making Same, and Information Handling System Utilizing Same
Circuitized Substrate Assembly and Method of Making Same
Low Moisture Absorptive Circuitized Substrate, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Information Handling System Utilizing Circuitized Substrate
High Speed Circuitized Substrate with Reduced Thru-Hole Stub, Method for Fabrication and Information Handling System Utilizing Same
Method of Making a Circuitized Substrate Having a Plurality of Solder Connection Sites Thereon
Capacitor Material with Metal Component for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate
Patent:
7,025,607 →
Application:
11/031,074 →
Capacitor Material for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate
Low Moisture Absorptive Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Electronic Card Assembly
Interposer for Use with Test Apparatus
Method of Making an Internal Capacitive Substrate for Use in a Circuitized Substrate and Method of Making Said Circuitized Substrate
Method of Making Multilayered Circuitized Substrate Assembly Having Sintered Paste Connections
Circuitized Substrate with Sintered Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same
Method and Apparatus for Depositing Conductive Paste in Circuitized Substrate Openings
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Circuitized Substrate with Soler-Coated Microparticle Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same and Method of Making Said Substrate
Substrate Test Apparatus and Method of Testing Substrates
Patent:
7,129,732 →
Application:
11/281,456 →
Method of Improving Electrical Connections in Circuitized Substrates
Method of Making Circuitized Substrate
Method of Treating Conductive Layer for Use in a Circuitized Substrate and Method of Making Said Substrate Having Said Conductive Layer as Part Thereof
Method of Making Circuitized Substrate
Method of Making Circuitized Substrate Assembly
Information Handling System Including a Circuitized Substrate Having a Dielectric Layer Without Continuous Fibers
Method of Making a Capacitive Substrate for Use as Part of a Larger Circuitized Substrate, Method of Making Said Circuitized Substrate and Method of Making an Information Handling System Including Said Circuitized Substrate
Fluoropolymer Dielectric Composition for Use in Circuitized Substrates and Circuitized Substrate Including Same
Method of Providing Printed Circuit Board with Conductive Holes and Board Resulting Therefrom
Circuitized Substrate with Shielded Signal Lines and Plated-Thru-Holes and Method of Making Same, and Electrical Assembly and Information Handling System Utilizing Same
Method of Making Circuitized Substrate with Signal Wire Shielding
Capacitive Substrate
High Speed Interposer
Method of Making a Multi-Chip Electronic Package Having Laminate Carrier
Circuitized Substrate Assembly
Halogen-Free Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Multilayered Substrate Structure Utilizing Same, and Information Handling System Utilizing
Method of Making a Circuitized Substrate with Enhanced Circuitry and Electrical Assembly Utilizing Said Substrate
Method of Making Circuitized Substrate with Solder Paste Connections
Interposer and Test Assembly for Testing Electronic Devices
Method of Making Circuitized Substrate with Split Conductive Layer and Information Handling System Utilizing Same
Method of Providing a Printed Circuit Board with an Edge Connection Portion and/or a Plurality of Cavities Therein
Method of Making Circuitized Substrate with Selected Conductors Having Solder Thereon
Led Lighting Assembly and Lamp Utilizing Same
Method of Making Same Low Moisture Absorptive Circuitized Substrave with Reduced Thermal Expansion
Circuitized Substrate with Internal Stacked Semiconductor Chips, Method of Making Same, Electrical Assembly Utilizing Same and Information Handling System Utilizing Same
Circuitized Substrate with Conductive Paste, Electrical Assembly Including Said Circuitized Substrate and Method of Making Said Substrate
Circuitized Substrate with Internal Resistor, Method of Making Said Circuitized Substrate, and Electrical Assembly Utilizing Said Circuitized Substrate
Method of Providing a Printed Circuit Board with an Edge Connection Portion
Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers
Method of Making an Interposer
Method of Making Multilayered Circuitized Substrate Assembly
Method of Making Circuitized Substrate with Internal Optical Pathway Using Photolithography
Method of Making Circuitized Substrate with Internal Optical Pathway
Circuitized Substrate with Internal Cooling Structure and Electrical Assembly Utilizing Same
Information Handling System Utilizing Circuitized Substrate with Split Conductive Layer
High Speed Interposer
Multilayered Circuitized Substrate with P-Aramid Dielectric Layers and Method of Making Same
Circuitized Substrate with Continuous Thermoplastic Support Film Dielectric Layers
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Capacitive Substrate and Method of Making Same
Method of Making Halogen-Free Circuitized Substrate with Reduced Thermal Expansion
Method of making a circuitized substrate
Electronic Package Including High Density Interposer and Circuitized Substrate Assembly Utilizing Same
Method of Making High Density Interposer and Electronic Package Utilizing Same
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Coreless Layer Buildup Structure
Coreless Layer Buildup Structure with Lga
Coreless Layer Buildup Structure with Lga and Joining Layer
Power Core for Use in Circuitized Substrate and Method of Making Same
Semi-Conductor Chip with Compressible Contact Structure and Electronic Package Utilizing Same
A Method of Joining a Semiconductor Device/Chip to a Printed Wiring Board
Conducting Paste for Device Level Interconnects
Method of Forming Multilayer Capacitors in a Printed Circuit Substrate
Circuitized Substrate with Dielectric Interposer Assembly and Method
A Method of Forming an Electrically Conductive Printed Line
Patent:
8,499,445 →
Application:
13/184,699 →
Circuitized Substrate with Low Loss Capacitive Material and Method of Making Same
Patent:
8,446,707 →
Application:
13/269,770 →
Solder and Electrically Conductive Adhesive Based Interconnection for Czt Crystal Attach
Patent:
8,592,299 →
Application:
13/358,716 →
Substrate Having Internal Capacitor and Method of Making Same
Patent:
8,607,445 →
Application:
13/517,776 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
Assignment of Assignor's Interest
Nov 4, 2020
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 054269/0366 →
Patent Security Agreement (Abl)
May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
Patent Security Agreement (Term Loan)
May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
Release of Security Interest in Patents Previously Recorded at Reel/Frame (063804/0702)
Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →