IP Library Granted Patent US 7,342,183
Granted Patent B2
US 7,342,183 · App. 11/177,442 · Granted Mar 11, 2008

Circuitized substrate with sintered paste connections, multilayered substrate assembly, electrical assembly and information handling system utilizing same

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Quick Facts
Patent No.
US 7,342,183
App. No.
11/177,442
Granted
Mar 11, 2008
Kind
B2
Abstract

A circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.

Claims (29)

1. A circuitized substrate comprising:

at least one high temperature dielectric layer having first and second opposing surfaces;

at least one opening within said at least one high temperature dielectric layer extending from said first opposing surface to said second opposing surface; and

a quantity of low temperature conductive paste positioned within said at least one opening and including an organic binder component and at least one metallic component including a plurality of flakes, said flakes being sintered and of such density within said paste so as to form at least one electrical path through said paste from said first opposing surface to said second opposing surface.

2. The circuitized substrate of claim 1 in which said at least one high temperature dielectric layer is comprised of a PTFE composite material.

3. The circuitized substrate of claim 1 wherein said organic binder is a resin.

4. The circuitized substrate of claim 3 wherein said resin is an anhydride epoxide.

5. The circuitized substrate of claim 1 wherein said at least one metallic component is selected from the group consisting of silver, copper and aluminum.

6. A multilayered circuitized substrate assembly comprising:

a first circuitized substrate including at least one high temperature dielectric layer having first and second opposing surfaces, at least one opening within said at least one high temperature dielectric layer extending from said first opposing surface to said second opposing surface, and a quantity of low temperature conductive paste positioned within said at least one opening and including an organic binder component and at least one metallic component including a plurality of flakes, said flakes being sintered and of such density within said paste so as to form at least one electrical path through said paste from said first opposing surface to said second opposing surface; and

a second circuitized substrate including at least one high temperature dielectric layer having first and second opposing surfaces and at least one conductive layer on said first opposing surface, said first and second circuitized substrates being bonded together such that said low temperature conductive paste within said at least one opening of said first circuitized substrate is electrically coupled to said at least one conductive layer of said second circuitized substrate.

7. The multilayered circuitized substrate assembly of claim 6 in which said at least one high temperature dielectric layer of each of said first and second circuitized substrates is comprised of a PTFE composite material.

8. The multilayered circuitized substrate assembly of claim 6 wherein said organic binder of said conductive paste within said opening of said first circuitized substrate is a resin.

9. The multilayered circuitized substrate assembly of claim 8 wherein said resin is an anhydride epoxide.

10. The multilayered circuitized substrate assembly of claim 6 wherein said at least one metallic component of said conductive paste within said opening of said first circuitized substrate is selected from the group consisting of silver, copper and aluminum.

11. The multilayered circuitized substrate assembly of claim 6 wherein said second circuitized substrate includes at least one thru-hole therein electrically coupled to said at least one conductive layer, said conductive paste being electrically coupled to said at least one thru-hole.

12. The multilayered circuitized substrate assembly of claim 6 further including a third circuitized substrate having at least one high temperature dielectric layer having first and second opposing surfaces and at least one conductive layer on said second opposing surface, said third circuitized substrate being bonded to said first circuitized substrate such that said low temperature conductive paste within said at least one opening of said first circuitized substrate is electrically coupled to said at least one conductive layer of said third circuitized substrate so as to electrically couple said at least one conductive layer of said second circuitized substrate with said at least one conductive layer of said third circuitized substrate.

13. An electrical assembly comprising:

a first circuitized substrate including at least one high temperature dielectric layer having first and second opposing surfaces, at least one opening within said at least one high temperature dielectric layer extending from said first opposing surface to said second opposing surface, and a quantity of low temperature conductive paste positioned within said at least one opening and including an organic binder component and at least one metallic component including a plurality of flakes, said flakes being sintered and of such density within said paste so as to form at least one electrical path through said paste from said first opposing surface to said second opposing surface; and

at least one electrical component electrically coupled to said low temperature conductive paste.

14. The electrical assembly of claim 13 wherein said at least one electrical component is a semiconductor chip.

15. The electrical assembly of claim 13 wherein said at least one electrical component is a chip carrier having at least one semiconductor chip as part thereof.

16. An information handling system comprising:

a housing;

a circuitized substrate positioned within said housing and including at least one high temperature dielectric layer having first and second opposing surfaces, at least one opening within said at least one high temperature dielectric layer extending from said first opposing surface to said second opposing surface, and a quantity of low temperature conductive paste positioned within said at least one opening and including an organic binder component and at least one metallic component including a plurality of flakes, said flakes being sintered and of such density within said paste so as to form at least one electrical path through said paste from said first opposing surface to said second opposing surface; and

at least one electrical component electrically coupled to said low temperature conductive paste.

17. The invention of claim 16 wherein said information handling system comprises a personal computer.

18. The invention of claim 16 wherein said information handling system comprises a mainframe computer.

19. The invention of claim 16 wherein said information handling system comprises a computer server.

Assignments (14)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2005
From: EGITTO, FRANK D.; MARKOVICH, VOYA R.; MATIENZO, LUIS J.
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 016777/0729 →