Patent Assignment
Reel/Frame 063804/0745
Patent Security Agreement (Term Loan)
Recorded: 2023-05-30
Pages: 24
Assignors
TELEPHONICS CORPORATION
Executed: 2023-05-30
TTM TECHNOLOGIES, INC.
Executed: 2023-05-30
TTM TECHNOLOGIES NORTH AMERICA, LLC
Executed: 2023-05-30
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
10 S. DEARBORN, FLOOR L2, CHICAGO, ILLINOIS, 60603
Covered Properties
(149)
Pcb Embedded and Surface Mounted Optical Distribution Systems
Fiber Optic Circuit Board Connector
Integrated Circuit Heat Sink Device Including Through Hole to Facilitate Communication
Bending an Optical Fiber into a Backplane
System and Method for Integrating Optical Layers in a Pcb for Inter-Board Communications
Quadrifilar Antenna Serial Feed
Multiport Serial Feed Device
System and Method for Electrolytic Plating
Circuitized Substrate Assembly and Method of Making Same
Information Handling System Utilizing Circuitized Substrate
Electronic Package with Strengthened Conductive Pad
Pinned Electronic Package with Strengthened Conductive Pad
Circulator and Method of Manufacture
Method for Analyzing Material Density Variations on a Multi-Layer Printed Circuit Board
Bending an Optical Fiber into Backplane
Electronic Component Test Apparatus
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Non-Switching Adaptable 4-Way Power Splitter/Combiner
Method of making multilayered printed circuit board with filled conductive holes
Printed Circuit Board with Low Cross-Talk Noise
Circuitized Substrate with Signal Wire Shielding, Electrical Assembly Utilizing Same and Method of Making
Dielectric Composition for Forming Dielectric Layer for Use in Circuitized Substrates
Circuitized Substrate
Fiber Optic Circuit Connector
Auxiliary Amplifier Network
Circuitized Substrate with Split Conductive Layer, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Circuitized Substrate with Filled Isolation Border, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Circuitized Substrate Assembly and Method of Making Same
Low Moisture Absorptive Circuitized Substrate, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Information Handling System Utilizing Circuitized Substrate
Method of Making a Circuitized Substrate Having a Plurality of Solder Connection Sites Thereon
Capacitor Material with Metal Component for Use in Circuitized Substrates, Circuitized Substrate Utilizing Same, Method of Making Said Circuitized Substrate, and Information Handling System Utilizing Said Circuitized Substrate
Patent:
7,025,607 →
Application:
11/031,074 →
Low Moisture Absorptive Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Electrical Assembly Utilizing Same, and Information Handling System Utilizing Same
Interposer for Use with Test Apparatus
Method of Making Multilayered Circuitized Substrate Assembly Having Sintered Paste Connections
Circuitized Substrate with Sintered Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same
System and Method for Suppressing Iff Responses in the Sidelobes and Backlobes of Iff Interrogator Antennas
Step Frequency High Resolution Radar
Method and Apparatus for Depositing Conductive Paste in Circuitized Substrate Openings
Stacked Chip Electronic Package Having Laminate Carrier and Method of Making Same
Circuitized Substrate with Soler-Coated Microparticle Paste Connections, Multilayered Substrate Assembly, Electrical Assembly and Information Handling System Utilizing Same and Method of Making Said Substrate
Dual Channel Spatially Adaptive Cfar
Substrate Test Apparatus and Method of Testing Substrates
Patent:
7,129,732 →
Application:
11/281,456 →
Method of Treating Conductive Layer for Use in a Circuitized Substrate and Method of Making Said Substrate Having Said Conductive Layer as Part Thereof
Method of Making Circuitized Substrate
Method of Making Circuitized Substrate Assembly
Information Handling System Including a Circuitized Substrate Having a Dielectric Layer Without Continuous Fibers
A Method for Detecting a Target
Method of Providing Printed Circuit Board with Conductive Holes and Board Resulting Therefrom
Circuitized Substrate with Shielded Signal Lines and Plated-Thru-Holes and Method of Making Same, and Electrical Assembly and Information Handling System Utilizing Same
Vertical Inter-Digital Coupler
Method of Making a Multi-Chip Electronic Package Having Laminate Carrier
Halogen-Free Circuitized Substrate with Reduced Thermal Expansion, Method of Making Same, Multilayered Substrate Structure Utilizing Same, and Information Handling System Utilizing
Method of Making a Circuitized Substrate with Enhanced Circuitry and Electrical Assembly Utilizing Said Substrate
Method of Making Circuitized Substrate with Solder Paste Connections
Method of Providing a Printed Circuit Board with an Edge Connection Portion and/or a Plurality of Cavities Therein
Inverted Style Balun with Dc Isolated Differential Ports
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Method of Making Same Low Moisture Absorptive Circuitized Substrave with Reduced Thermal Expansion
Circuitized Substrate with Internal Stacked Semiconductor Chips, Method of Making Same, Electrical Assembly Utilizing Same and Information Handling System Utilizing Same
Circuitized Substrate with Conductive Paste, Electrical Assembly Including Said Circuitized Substrate and Method of Making Said Substrate
Method of Providing a Printed Circuit Board with an Edge Connection Portion
Surface Mount Stripline Devices Having Ceramic and Soft Board Hybrid Materials
Circuitized substrate with dielectric layer having dielectric composition not including continuous or semi-continuous fibers
Method of Making an Interposer
Method of Making Circuitized Substrate with Internal Optical Pathway
Circuitized Substrate with Internal Cooling Structure and Electrical Assembly Utilizing Same
High Speed Interposer
Method of Manufacturing a Printed Circuit Board
Multilayered Circuitized Substrate with P-Aramid Dielectric Layers and Method of Making Same
Circuitized Substrate with Continuous Thermoplastic Support Film Dielectric Layers
Method of Manufacturing a Multilayer Printed Wiring Board with Copper Wrap Plated Hole
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Capacitive Substrate and Method of Making Same
Method of Making Halogen-Free Circuitized Substrate with Reduced Thermal Expansion
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Coupler Device
Patent:
8,044,749 →
Application:
12/392,649 →
System for Cleaning Components for Filling Holes in a Printed Circuit Board with a Fluid Fill Material
Manufacturing Methods of Multilayer Printed Circuit Board Having Stacked Via
Compact Balun
Method of Making High Density Interposer and Electronic Package Utilizing Same
Multi-Layer Embedded Capacitance and Resistance Substrate Core
Surface Mountable Circulator
Coreless Layer Buildup Structure with Lga
Methods of Manufacturing Printed Circuit Boards
Patent:
8,020,292 →
Application:
12/772,086 →
Power Core for Use in Circuitized Substrate and Method of Making Same
A Method of Joining a Semiconductor Device/Chip to a Printed Wiring Board
Magnetic Instrument Pickup
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Methods of Manufacturing Printed Circuit Boards
Methods of Manufacturing Printed Circuit Boards Using Parallel Processes to Interconnect with Subassemblies
Wideband Balun Using Re-Entrant Coupled Lines and Ferrite Material
Impedance Transforming Coupler
Method of Making a Circuitized Substrate
Methods of Manufacturing a Printed Wiring Board Having Copper Wrap Plated Hole
Printed Circuit Board with Embedded Heater
Circuit Board Multi-Functional Hole System and Method
Doherty Power Amplifier Network
Compact Broadband Impedance Transformer
Wideband Doherty Amplifier Network
Rf Resistor with Lossy Traces
First and Second Microstrip Networks Stacked in an Inverted Arrangement to Each Other Using an Integrated Support and Shielding Structure
Hybrid Coupler Device Having Plural Transmission Line Structures with Unwound-Rewound Geometry
Method of Fabricating a Printed Circuit Board Interconnect Assembly
High Power RF Circuit
Patent:
8,969,733 →
Application:
14/041,155 →
Systems and Methods of Manufacturing Printed Circuit Boards Using Blind and Internal Micro Vias to Couple Subassemblies
Stress Relieved High Power Rf Circuit
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Bidirectional Integrated Cmos Switch
Self-Cascadable Phase Shifter
Method for Anchoring a Conductive Cap on a Filled via in a Printed Circuit Board and Printed Circuit Board with an Anchored Conductive Cap
Wideband Rf Device
Rf Attenuator Device and System
Rf Termination
Impedance Matching Component
Circulator with Modified Bias to Prevent Higher Order Modes
High Powered Rf Part for Improved Manufacturability
Wideband Gysel Power Divider
System and Method for Providing Accurate Position Location Information to Military Forces in a Disadvantaged Signal Environment
Patent:
10,591,609 →
Application:
15/866,849 →
Bidirectional Integrated Cmos Switch
Air-Cooled Heat Exchanger and Thermal Arrangement for Stacked Electronics
Patent:
10,757,809 →
Application:
16/203,999 →
Compact Radar with X Band Long-Distance Weather Monitoring & W Band High-Resolution Obstacle Imaging for Landing in a Degraded Visual Environment
Patent:
11,493,622 →
Application:
16/270,046 →
Methods for Fabricating Printed Circuit Board Assemblies with High Density via Array
Wideband Termination for High Power Applications
Patent:
10,772,193 →
Application:
16/705,703 →
Directional Couplers with Dc Insulated Input and Output Ports
System and Method for Providing Accurate Position Location Information to Military Forces in a Disadvantaged Signal Environment
Air-Cooled Heat Exchanger and Thermal Arrangement for Stacked Electronics
Wideband Termination for High Power Applications
Three-Dimensional Circuit Assembly with Composite Bonded Encapsulation
High-Density Optical Waveguide Structure and Printed Circuit Board and Preparation Method Thereof
Monopulse Secondary Surveillance Radar System
Patent:
11,320,528 →
Application:
17/088,768 →
Systems and Methods for Removing Undesired Metal Within Vias from Printed Circuit Boards
Gps Denial Detection and Reporting and Mitigation
Patent:
11,698,461 →
Application:
17/121,853 →
Method of Manufacturing Printed Circuit Board Assemblies with Engineered Thermal Paths
Vacuum Nozzle Assembly for Vacuum-Assisted Driver
Application:
17/191,480 →
Publication:
US 2021/0276167
Methods for Fabricating Printed Circuit Board Assemblies with High Density via Array
Application:
17/225,491 →
Publication:
US 2021/0227695
High Powered Rf Part for Improved Manufacturability
Systems and Methods for Removing Undesired Metal Within Vias from Printed Circuit Boards
Application:
17/511,333 →
Publication:
US 2022/0053641
Methods for Forming Engineered Thermal Paths of Printed Circuit Boards by Use of Removable Layers
AESA True Dual Beam Full Range, Full Doppler Spectrum Imaging While Scanning Radar System
Patent:
12,523,756 →
Application:
17/543,891 →
Near-Hermetic Package with Flexible Signal Input and Output
High Powered Rf Part for Improved Manufacturability
Application:
17/725,371 →
Publication:
US 2022/0247058
Forming Waveguides and Heat Transfer Elements in Printed Circuit Boards
Application:
17/939,786 →
Publication:
US 2023/0082429
Circulator Design and Methods of Fabricating the Circulator
Shielded Signal Vias in Printed Circuit Boards for High-Frequency and Broadband Signals
Application:
18/121,355 →
Publication:
US 2023/0292431
System and Methods for Passive Alignments of Light Transmitting or Receiving Devices to Planar Waveguides
Application:
63/449,520 →
Folded Circulator Device with Coupling Elements and Flex Connections for Interconnect and Methods of Fabricating the Circulator Device
Application:
63/452,736 →
Fast Switching, Ultra-Low Power and Compact Varactor Driver
Application:
63/460,554 →
Systems and Methods for Baluns Optimized for Wideband Balanced Properties
Application:
63/476,539 →
Related Assignments
(15)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
Release of Second Lien Security Interest in Intellectual Property Recorded at Reel/Frame: 032276/0179
Apr 18, 2018
From: CREDIT SUISSE AG, AS COLLATERAL AGENT
To: ANAREN, INC.; ANAREN MICROWAVE, INC.
Reel/Frame 045972/0001 →
Release of First Lien Security Interest in Intellectual Property Recorded at Reel/Frame 032275/0473
Apr 18, 2018
From: CREDIT SUISSE AG, AS COLLATERAL AGENT
To: ANAREN, INC.; ANAREN MICROWAVE, INC.
Reel/Frame 045978/0510 →
Supplement to Patent Security Agreement - Tl
Apr 23, 2018
From: ANAREN, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046000/0815 →
Supplement to Patent Security Agreement - Abl
Apr 23, 2018
From: ANAREN, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 045998/0401 →
Assignment of Assignor's Interest
Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
Merger
Sep 9, 2019
From: VIASYSTEMS GROUP, INC.
To: TTM TECHNOLOGIES, INC.
Reel/Frame 050313/0926 →
Merger
Sep 9, 2019
From: VIASYSTEMS, INC.
To: VIASYSTEMS GROUP, INC.
Reel/Frame 050313/0826 →
Assignment of Assignor's Interest
Nov 4, 2020
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 054269/0366 →
Assignment of Assignor's Interest
Jun 23, 2021
From: ANAREN, INC.
To: TTM TECHNOLOGIES INC.
Reel/Frame 056635/0640 →
Merger
May 12, 2023
From: VIASYSTEMS GROUP, INC.
To: TTM TECHNOLOGIES, INC.
Reel/Frame 063629/0313 →
Merger
May 12, 2023
From: VIASYSTEMS, INC.
To: VIASYSTEMS GROUP, INC.
Reel/Frame 063628/0122 →
Patent Security Agreement (Abl)
May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
Release of Security Interest in Patents Previously Recorded at Reel/Frame (035858/0890)
Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
Release of Security Interest in Patents Previously Recorded at Reel/Frame (063804/0702)
Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →