IP Library Granted Patent US 11,158,920
Granted Patent B2
US 11,158,920 · App. 15/486,361 · Granted Oct 26, 2021

High powered RF part for improved manufacturability

Inventors: Michael Len (Skaneateles, NY); Hans Peter Ostergaard (Viborg, DK)
Assignee: TTM Technologies Inc.
H01P1/30H01P5/187H05K1/0203H05K1/0243H05K1/0204H05K1/0215H05K1/0251H05K1/0306H05K3/3431H05K3/3442
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,158,920
App. No.
15/486,361
Granted
Oct 26, 2021
Kind
B2
Abstract

An electrical component, such as an RF device or thermal bridge, for use with a printed circuit board. The component has a first dielectric layer having a top and a bottom, a first conductive trace positioned on the bottom of the dielectric layer, and a first ground layer positioned on the bottom of the dielectric layer and spaced apart from the first conductive trace. For RF applications, a second conductive trace is positioned on top of first dielectric, a second dielectric is positioned on top of the second conductive trace, and a second ground plane is positioned on top of the second dielectric. A printed circuit board having a third conductive trace may then be coupled to the first conductive trace by a first solder layer.

Claims (35)

1. An electrical component for a printed circuit board, comprising:

a first dielectric layer having a top and a bottom;

a first conductive trace positioned on the bottom of the first dielectric layer;

a first ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace, wherein the first conductive trace is aligned with a second conductive trace of the printed circuit board along a full length of the first conductive trace;

a first solder layer connecting the first conductive trace to the second conductive trace of the printed circuit board and extending the full length of the first conductive trace, wherein the second conductive trace comprises a transmission line and is a portion of the electrical component;

a second solder layer connecting the first ground layer to an upper ground layer of the printed circuit board;

a third conductive trace over the top of the first dielectric layer, wherein the first conductive trace and the third conductive trace are wider than the transmission line; and

wherein the upper ground layer is spaced apart from the second conductive trace on top of the printed circuit board, wherein the electrical component has a thermal path comprising the first solder layer.

2. The component of claim 1 , further comprising a first ground plane positioned on the top of the first dielectric layer and including at least one via spanning the first dielectric layer.

3. The component of claim 2 , further comprising a second ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace and the first ground layer.

4. The component of claim 3 , wherein the first dielectric layer has a high thermal conductivity.

5. The component of claim 1 , wherein the first dielectric layer is formed from a ceramic material.

6. The component of claim 5 , wherein the ceramic material is selected from the group consisting of AlN and Al 2 O 3 .

7. The component of claim 6 , wherein the ceramic material is a thermal bridge.

8. The component of claim 1 , wherein the thermal path further comprises the first conductive trace, the second conductive trace of the printed circuit board, and the first dielectric layer.

9. The component of claim 1 , further comprising a second dielectric layer over the third conductive trace.

10. The component of claim 1 , wherein the third conductive trace is connected to a plurality of device pads, and the first solder layer does not connect to the plurality of device pads.

11. The component of claim 10 , wherein the third conductive trace is coupled to signal outputs formed by the plurality of device pads coupled to a corresponding plurality of contact regions of the printed circuit board via the second solder layer.

12. An electrical component for a printed circuit board, comprising:

a first dielectric layer having a top and a bottom;

a first conductive trace positioned on the bottom of the first dielectric layer;

a first ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace, wherein the first conductive trace is aligned with a second conductive trace of the printed circuit board along a full length of the first conductive trace;

a third conductive trace positioned on the top of the first dielectric layer;

a second dielectric layer positioned on top of the third conductive trace;

a first solder layer connecting the first conductive trace to the second conductive trace of the printed circuit board and extending the full length of the first conductive trace, wherein the second conductive trace comprises a transmission line and is a portion of the electrical component, wherein the first conductive trace and the third conductive trace are wider than the transmission line; and

a second solder layer connecting the first ground layer to a second ground layer spaced apart from the second conductive trace, wherein the second ground layer and the second conductive trace are on top of the printed circuit board, wherein the electrical component has a thermal path comprising the first solder layer.

13. The component of claim 12 , further comprising a second ground plane positioned on top of the second dielectric layer and including at least one via spanning the second dielectric layer.

14. The component of claim 13 , wherein the printed circuit board further includes a third dielectric layer supporting a third conductive trace and a second ground plane positioned on an opposing side of the third dielectric layer.

15. The component of claim 14 , wherein the printed circuit board further includes at least one interconnection via formed through the third dielectric layer.

16. The component of claim 12 , further comprising a set of ground vias positioned on either side of the transmission line.

17. The component of claim 16 , wherein the printed circuit board further includes a plurality of signal contact regions.

18. The component of claim 17 , wherein the plurality of signal contact regions is coupled to a corresponding plurality of device pads associated with the first conductive trace, wherein the first solder layer does not connect to the plurality of device pads.

19. The component of claim 18 , wherein the component is an RF device.

20. The component of claim 14 , wherein the thermal path further comprises the first conductive trace, the second conductive trace of the printed circuit board, and the first dielectric layer.

21. The component of claim 18 , wherein the third conductive trace is coupled to signal outputs formed by the plurality of signal contact regions of the printed circuit board coupled to the corresponding plurality of device pads via the second solder layer.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: ANAREN, INC.
To: TTM TECHNOLOGIES INC.
Reel/Frame 056635/0640 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT - ABL Recorded Apr 23, 2018
From: ANAREN, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 045998/0401 →
SUPPLEMENT TO PATENT SECURITY AGREEMENT - TL Recorded Apr 23, 2018
From: ANAREN, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046000/0815 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2017
From: LEN, MICHAEL; OSTERGAARD, HANS PETER
To: ANAREN, INC.
Reel/Frame 041994/0823 →
Continuity (3)
Provisional Application 62327839 · Apr 26, 2016
Provisional Application 62338281 · May 18, 2016
Related Publication 20170309983A1 · Oct 26, 2017