Bidirectional integrated CMOS switch
View Patent ↗A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices.
1. A bidirectional integrated CMOS switch comprising:
a diode bridge comprising a first diode (DO), a second diode (D 1 ), a third diode (D 2 ), and a fourth diode (D 3 );
a first switch terminal (A) coupled to said diode bridge between said fourth diode (D 3 ) and said first diode (D 0 );
a second switch terminal (B) coupled to said diode bridge between said second diode (D 1 ) and said third diode (D 2 ):
a first NMOS transistor (M 0 ), and a first PMOS transistor (M 1 ), configured as a transmission gate, with each said transistor comprising a parasitic body diode oriented in the same direction, wherein a source of said first PMOS transistor (M 1 ) and a drain of said first NMOS transistor (M 0 ) are each respectively coupled to said diode bridge between said first diode (D 0 ) and said third diode (D 2 ) to form a first node (C), and wherein a drain of said first PMOS transistor (M 1 ) and a source of said first NMOS transistor (M 0 ) are each respectively coupled to said diode bridge between said second diode (D 1 ) and said fourth diode (D 3 ) to form a second node (D);
a 5 volt logic inverter;
wherein said diode bridge, said logic inverter, said first NMOS transistor (M 0 ), and said first PMOS transistor (M 1 ) are coupled to form a conduction path to cause current to flow from either of said first and second switch terminals (A/B) through said switch in only one direction, from said first node (C) to said second node (D), regardless of a voltage polarity on said first and second switch terminals (A/B), to prevent said body diodes from being forward biased;
a plurality of control circuitry elements comprising:
a first clamp, said first clamp coupled across a gate and a source of said first NMOS transistor (M 0 ) to limit gate-to-source voltage of said first NMOS transistor (M 0 );
a second PMOS transistor (M 2 ), a fifth diode (D 4 ), and a first resistor (R 1 ) connected from said gate of said first NMOS transistor (M 0 ) to said logic inverter, to form a primary on/off control for said first NMOS transistor (M 0 ); wherein when a gate of said second PMOS transistor (M 2 ) is pulled low, said second PMOS transistor (M 2 ) is turned on and current flows through said second PMOS transistor (M 2 ), said fifth diode (D 4 ), and said first resistor (R 1 ), to pull up said gate of said first NMOS transistor (M 0 ); wherein said first resistor (R 1 ) is configured to minimize bias current flow to said second node (D); and wherein when said gate of said second PMOS transistor (M 2 ) is pulled high, said second PMOS transistor (M 2 ) is turned off and gate-source voltage of said first NMOS transistor (M 0 ) is discharged through said first clamp and drops to zero, to turn off said first NMOS transistor (M 0 );
a second clamp, said second clamp coupled across a gate and a source of said first PMOS transistor (M 1 ) to limit gate-to-source voltage of said first PMOS transistor (M 1 );
a third PMOS transistor (M 11 ), a sixth diode (D 9 ) and a second resistor (R 6 ) connected from said gate of said first PMOS transistor (M 1 ) to said logic inverter, to form a primary on/off control for said first PMOS transistor (M 1 ); wherein when a gate of said third PMOS transistor (M 11 ) is pulled low, said third PMOS transistor (M 11 ) is turned on and current flows through said third PMOS transistor (M 11 ), said sixth diode (D 9 ), and said second resistor (R 6 ), to pull up said gate of said first PMOS transistor (M 1 ); wherein when the gate of said third PMOS transistor (M 11 ) is pulled high, said third PMOS transistor (M 11 ) is turned off, and gate-source voltage of said first PMOS transistor (M 1 ) is discharged through said second clamp, and drops to zero, to turn off said first PMOS transistor (M 1 ); and
wherein said plurality of control circuitry elements are configured to turn said switch on and off using low voltage supplies that are compatible with gate source voltages needed to turn on said first NMOS transistor (M 0 ) and said first PMOS transistor (M 1 ).
2. The switch according to claim 1 wherein said switch is formed with a high voltage silicon-on-insulator manufacturing process with deep trench isolation, with each of said diodes of said bridge isolated in individual wells, with a non-conductive material under and around each side of a body of each said diode; with each of said NMOS and PMOS transistors isolated in individual wells with a non-conductive material under and around each side of a body of each of said NMOS transistors and a body of each of said PMOS transistors, and with each of said plurality of control circuitry elements isolated in individual wells with a non-conductive material under and around each side of a body of each of said control circuitry elements.