IP Library Granted Patent US 12,262,464
Granted Patent B2
US 12,262,464 · App. 17/543,512 · Granted Mar 25, 2025

Methods for forming engineered thermal paths of printed circuit boards by use of removable layers

Inventors: Matthew D. Neely (Santa Ana, CA); Michael Len (Santa Ana, CA); King Yip Leung (Santa Ana, CA)
H05K1/0206H05K1/115H05K3/0026H05K3/0047H05K3/422H05K3/423H05K3/0038H05K2203/0542H05K2203/072H05K2203/0723H05K2203/1572
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Quick Facts
Patent No.
US 12,262,464
App. No.
17/543,512
Granted
Mar 25, 2025
Kind
B2
Abstract

A method for forming a thermal and electrical path in a PCB may include forming a first removable layer over a top surface of a PCB and a second removable layer over a bottom surface of the PCB. The method may also include milling or laser drilling the PCB from the top surface to form a first cavity extending into the PCB, plating the first side panel plating the first side with a second metal to partially fill the first cavity; and milling or laser drilling from the bottom surface to form a second cavity extending into the PCB, the first cavity in a thermal communication and/or an electrical communication with the second cavity. The method may also include panel plating the first side with a second metal to fill the first cavity and the second side with the second metal to fill the second cavity, and removing the first and second removable layers from the PCB to form the PCB with a thermal and/or an electrical path comprising the first cavity and the second cavity filled with the second metal.

Claims (31)

1. A method of forming a thermal and/or an electrical path in a PCB, the method comprising:

forming a first removable layer over a top surface of a PCB and a second removable layer over a bottom surface of the PCB;

milling or laser drilling through both the first removable layer and the PCB from the top surface to form a first cavity extending into the PCB;

seed plating the PCB including the first cavity with a first seed plating material to form a first conductive coating;

initial panel plating the PCB with a metal to partially fill the first cavity;

milling or laser drilling through both the second removable layer and the PCB from the bottom surface to form a second cavity extending into the PCB, the first cavity in a thermal communication and/or an electrical communication with the second cavity;

seed plating the PCB including the second cavity with a second seed plating material to form a second conductive coating;

panel plating the PCB with the metal to fully fill the first cavity and the second cavity and form a first plated metal layer on a first exposed surface of the PCB and a second plated metal layer on a second exposed surface of the PCB; and

removing the first and second removable layers from the PCB to form the PCB with a thermal and/or an electrical path comprising the first cavity and the second cavity filled with the metal, wherein a cross sectional area of the filled first cavity or the filled second cavity larger than a cross sectional area of through-vias.

2. The method of claim 1 , wherein seed plating the PCB including the first cavity or the second cavity comprises electroless plating.

3. The method of claim 1 , wherein the thickness of the initial panel plating partially filling the first cavity ranges from 0.002 inches to 0.008 inches.

4. The method of claim 1 , wherein the first removable layer comprises a first fiber-reinforced prepreg layer over the top surface of the PCB and a first conductive foil over the first fiber-reinforced prepreg layer, wherein the second removable layer comprises a second fiber-reinforced prepreg layer under the bottom surface of the PCB and a second conductive foil under the second fiber-reinforced prepreg layer.

5. The method of claim 1 , the step of removing the first and second removable layers from the PCB comprising:

milling the first plated metal layer and the first removable layer near the first cavity to a first controlled depth in the first removable layer to separate the first plated metal connection between the PCB and the first removable layer;

removing the first removable layer from the PCB along with the remaining portion of the first plated metal layer after milling the first plated metal layer;

milling the second plated metal layer and the second removable layer near the second cavity to a second controlled depth in the second removable layer to separate the second plated metal connection between the PCB and the second removable layer; and

removing the second removable layer from the PCB along with the remaining portion of the second plated metal layer after milling the second plated metal layer.

6. The method of claim 5 , wherein each of the first and second controlled depths comprises a milled depth into the first or second removable layer that is equal to or less than half of the thickness of the respective first or second removable layer.

7. The method of claim 1 , further comprising planarizing the top and bottom surfaces of the PCB after removing the first and second removable layers from the PCB.

8. The method of claim 1 , further comprising drilling holes in the PCB to form drilled holes and plating the drilled holes after removing the first and second removable layers from the PCB.

9. The method of claim 1 , wherein each of the first and second removable layers comprises a thermoplastic material.

10. The method of claim 1 , wherein each of the first and second removable layers comprises a thermoset material.

11. The method of claim 1 , further comprising:

drilling through the first removable layer to form a drilled or milled portion; and

milling the first plated metal layer near the drilled or milled portion of the first removable layer to a first controlled depth in the first removable layer to form a conductive trace having a pattern defined by the drilled portion of the first removable layer.

12. The method of claim 1 , wherein panel plating the PCB comprises panel plating by a horizontal copper plating system to shorten plating time.

13. The method of claim 1 , wherein the cross sectional area of the filled first cavity or the filled second cavity is at least two times larger than the cross sectional area of through-vias.

14. The method of claim 1 , wherein the filled first cavity or filled second cavity functions as a copper coin.

15. The method of claim 1 , wherein the first cavity has the same dimensions as the second cavity.

16. The method of claim 1 , wherein the first cavity has a smaller or larger dimension than the second cavity.

17. The method of claim 1 , wherein the first cavity has different dimensions from the second cavity such that the thermal path and/or the electrical path have a cross-section having a T-shape.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME TO INCLUDE MISSING COMMA IN NAME PREVIOUSLY RECORDED ON REEL 059115 FRAME 0320. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 23, 2023
From: NEELY, MATTHEW D.; LEN, MICHAEL; LEUNG, KING YIP
To: TTM TECHNOLOGIES, INC.
Reel/Frame 063741/0181 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2022
From: NEELY, MATTHEW D.; LEN, MICHAEL; LEUNG, KING YIP
To: TTM TECHNOLOGIES INC.
Reel/Frame 059115/0320 →
Continuity (2)
Provisional Application 63123400 · Dec 9, 2020
Related Publication 20220183141A1 · Jun 9, 2022
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