IP Library Granted Patent US 12,176,592
Granted Patent B2
US 12,176,592 · App. 17/492,389 · Granted Dec 24, 2024

High powered RF part for improved manufacturability

Inventors: Michael Len (Skaneateles, NY); Hans Peter Ostergaard (Viborg, DK)
Assignee: TTM Technologies Inc.
H01P1/30H01P5/187H05K1/0203H05K1/0243H05K1/0204H05K1/0215H05K1/0251H05K1/0306H05K3/3431H05K3/3442
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Quick Facts
Patent No.
US 12,176,592
App. No.
17/492,389
Granted
Dec 24, 2024
Kind
B2
Abstract

An electrical component, such as an RF device or thermal bridge, for use with a printed circuit board. The component has a first dielectric layer having a top and a bottom, a first conductive trace positioned on the bottom of the dielectric layer, and a first ground layer positioned on the bottom of the dielectric layer and spaced apart from the first conductive trace. For RF applications, a second conductive trace is positioned on top of first dielectric, a second dielectric is positioned on top of the second conductive trace, and a second ground plane is positioned on top of the second dielectric. A printed circuit board having a third conductive trace may then be coupled to the first conductive trace by a first solder layer.

Claims (35)

1. An electrical component for a printed circuit board, comprising:

a first dielectric layer having a top and a bottom;

a first conductive trace positioned on the bottom of the first dielectric layer;

a first ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace, wherein the first conductive trace is aligned with a second conductive trace of the printed circuit board along a full length of the first conductive trace;

a first solder layer connecting the first conductive trace to the second conductive trace of the printed circuit board and extending the full length of the first conductive trace; and

a third conductive trace over the top of the first dielectric layer, wherein the third conductive trace is electrically isolated or DC isolated from the first conductive trace, wherein the third conductive trace is coupled to signal outputs formed by two or more signal contact regions of the printed circuit board.

2. The component of claim 1 , further comprising a first ground plane positioned on the top of the first dielectric layer and at least one via spanning the first dielectric layer.

3. The component of claim 2 , further comprising a second ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace and the first ground layer.

4. The component of claim 1 , further comprising a second solder layer connecting the first ground layer to an upper ground layer of the printed circuit board, wherein the upper ground layer is spaced apart from the second conductive trace on top of the printed circuit board.

5. The component of claim 4 , wherein the electrical component has a thermal path comprising the first conductive trace, the first dielectric layer, the first ground layer, the first solder layer, and the upper ground layer of the printed circuit board.

6. The component of claim 1 , further comprising a second dielectric layer over the third conductive trace; and a second ground plane over the second dielectric layer.

7. The component of claim 1 , wherein the second conductive trace comprises a transmission line and is a portion of the electrical component.

8. The component of claim 1 , wherein the first conductive trace is wider than the second conductive trace.

9. The component of claim 1 , wherein the first conductive trace is narrower than the second conductive trace.

10. The component of claim 1 , wherein the second conductive trace is narrower in a region where the second conductive trace overlaps with the first conductive trace than a remaining region.

11. The component of claim 1 , wherein the first conductive trace is wider than the third conductive trace.

12. An electrical component for a printed circuit board, comprising:

a first dielectric layer having a top and a bottom;

a first conductive trace positioned on the bottom of the first dielectric layer;

a first ground layer positioned on the bottom of the first dielectric layer and spaced apart from the first conductive trace, wherein the first conductive trace is aligned with a second conductive trace of the printed circuit board along a full length of the first conductive trace;

a third conductive trace over the top of the first dielectric layer;

a second dielectric layer positioned on top of the third conductive trace;

a first solder layer connecting the first conductive trace to the second conductive trace of the printed circuit board, and

a second solder layer connecting the first ground layer to an upper ground layer of the printed circuit board,

wherein the third conductive trace is electrically isolated or DC isolated from the first conductive trace, wherein the third conductive trace is coupled to signal outputs formed by two or more signal contact regions of the printed circuit board,

wherein the electrical component has a first thermal path dissipating heat via the printed circuit board and a second thermal path via the electrical component.

13. The component of claim 12 , further comprising a first ground plane positioned on top of the second dielectric layer and comprising at least one via spanning the first and second dielectric layer.

14. The component of claim 12 , wherein the second conductive trace is narrower in a region where the second conductive trace overlaps with the first conductive trace than a remaining region.

15. The component of claim 12 , wherein the first dielectric layer comprises a ceramic.

16. The component of claim 15 , wherein the ceramic material is one of AlN and Al 2 O 3 .

17. The component of claim 12 , further comprising a second ground plane over the second dielectric layer.

18. The component of claim 12 , wherein the first conductive trace is wider than the second conductive trace.

19. The component of claim 12 , wherein the second conductive trace comprises a transmission line and is a portion of the electrical component.

20. The component of claim 12 , wherein the first thermal path comprising the first solder layer, the second conductive trace, and a dielectric layer of the printed circuit board, and the second thermal path comprising the first dielectric layer, the second dielectric layer, the first ground layer, the second solder layer and the upper ground layer of the printed circuit board.

21. The component of claim 12 , wherein the first conductive trace is wider than the third conductive trace.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2023
From: LEN, MICHAEL; OSTERGAARD, HANS PETER
To: ANAREN, INC.
Reel/Frame 063675/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2023
From: ANAREN, INC.
To: TTM TECHNOLOGIES INC.
Reel/Frame 063675/0198 →