IP Library Granted Patent US 7,292,055
Granted Patent B2
US 7,292,055 · App. 11/110,901 · Granted Nov 6, 2007

Interposer for use with test apparatus

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Quick Facts
Patent No.
US 7,292,055
App. No.
11/110,901
Granted
Nov 6, 2007
Kind
B2
Abstract

An interposer including at least two dielectric layers bonded to each other, sandwiching a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts formed within and protruding from openings with the dielectric layers.

Claims (14)

1. An interposer comprising:

a first dielectric layer including a plurality of openings therein;

a first plurality of metallic contacts located within said plurality of openings within said first dielectric layer, selected ones of said first plurality of metallic contacts including a protruding portion protruding from said first dielectric layer;

a second dielectric layer bonded to said first dielectric layer and including a plurality of openings therein;

a second plurality of metallic contacts located within said plurality of openings within said second dielectric layer, selected ones of said second plurality of metallic contacts including a protruding portion protruding from said second dielectric layer in an opposing direction from said selected ones of said first plurality of metallic contacts protruding from said first dielectric layer, each of said selected ones of said first plurality of metallic contacts being positioned in an offsetting relationship with respect to a corresponding one of said selected ones of said second plurality of metallic contacts to form a paired contact location; and

a plurality of electrical conductors positioned substantially between said first and second dielectric layers, each of said electrical conductors electrically connecting selected ones of said first plurality of metallic contacts with respective ones of said selected ones of said second plurality of metallic contacts, said interposer, including said first and second dielectric layers, said first and second plurality of metallic contacts and said plurality of electrical conductors, being adapted for tilting at each of said paired contact locations of said first and second metallic contacts in response to the application of forces on said first and second metallic contacts at said paired locations to compensate for the application of said forces in an excessive manner.

2. The interposer of claim 1 wherein each of said first and second plurality of metallic contacts is comprised of copper.

3. The interposer of claim 1 wherein selected ones of said second plurality of metallic contacts include a sculpted configuration.

4. The interposer of claim 1 wherein selected ones of said first plurality of metallic contacts include a domed portion.

5. The interposer of claim 1 wherein said selected ones of said first plurality of metallic contacts include a first conductive plating thereon.

6. The interposer of claim 5 wherein said selected ones of said first plurality of metallic contacts include a second conductive plating substantially over said first conductive plating.

7. The interposer of claim 1 wherein selected ones of said first plurality of metallic contacts include a sculpted configuration and selected ones of said second plurality of metallic contacts include a domed configuration.

8. The interposer of claim 1 wherein selected ones of both said first and second plurality of metallic contacts include a domed configuration.

9. The invention of claim 1 wherein said interposer is adapted for use as part of a test apparatus for testing semiconductor chips having a plurality of contacts thereon, said first plurality of metallic contacts located within said plurality of openings within said first dielectric layer being adapted for engaging respective ones of said plurality of contacts on said semiconductor chip.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →