IP Library Granted Patent US 7,803,688
Granted Patent B2
US 7,803,688 · App. 12/380,616 · Granted Sep 28, 2010

Capacitive substrate and method of making same

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Quick Facts
Patent No.
US 7,803,688
App. No.
12/380,616
Granted
Sep 28, 2010
Kind
B2
Abstract

A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

Claims (25)

1. A method of making a capacitive substrate, said method comprising:

providing a first glass layer having a first surface and a second surface;

providing a first conductor on said first surface of said first glass layer;

positioning a capacitive dielectric layer on said first surface of said first glass layer and substantially over said first conductor using an ink jet printing process and substantially drying said capacitive dielectric layer at a predetermined temperature range;

providing a second conductor on said first capacitive dielectric layer;

positioning a second glass layer on said first capacitive dielectric layer and substantially over said second conductor, said second glass layer having a first surface;

forming a first thru-hole electrical connection to said first conductor; and

forming a second thru-hole electrical connection to said second conductor, said first and second conductors and said capacitive dielectric layer forming a capacitor when said capacitive substrate is in operation.

2. The method of claim 1 wherein said first and second conductors are provided using sputtering.

3. The method of claim 2 wherein the material of said first and second conductors is selected from the group consisting of gold, aluminum, chrome, titanium, platinum, copper, nickel and alloys thereof, and tin oxide, indium tin oxide and doped tin oxide.

4. The method of claim 1 further including forming a conductive member on said first surface of said first glass layer adjacent said first conductor, said positioning of said second glass layer on said first capacitive dielectric layer and substantially over said second conductor further including positioning said second glass layer substantially over said conductive member.

5. The method of claim 4 further including forming third and fourth thru-hole electrical connections to said conductive member.

6. The method of claim 5 wherein said first thru-hole electrical connection to said first conductor is formed through said first glass layer, said second thru-hole electrical connection to said second conductor is formed through said second glass layer, and said third and fourth thru-hole electrical connections are formed through said first and second glass layers, respectively, said method further including forming a first electrically conductive layer on said second surface of said first glass layer electrically coupled to said first and third thru-hole electrical connections and forming a second electrically conductive layer on said first surface of said second glass layer electrically coupled to said second and fourth thru-hole electrical connections.

7. The method of claim 1 wherein said first thru-hole electrical connection to said first conductor is formed through said first glass layer and said second thru-hole electrical connection to said second conductor is formed through said second glass layer, said method further including forming a first electrically conductive layer on said second surface of said first glass layer electrically coupled to said first thru-hole electrical connection and forming a second electrically conductive layer on said first surface of said second glass layer electrically coupled to said second thru-hole electrical connection.

8. The method of claim 7 further including forming additional dielectric layers and conductive layers on opposing sides of said first and second glass layers in an alternating manner.

9. A method of making a capacitive substrate, said method comprising:

providing a first glass layer having a first surface and a second surface;

providing a first conductor on said first surface of said first glass layer;

positioning a capacitive dielectric layer on said first surface of said first glass layer and substantially over said first conductor;

providing a second conductor on said first capacitive dielectric layer;

positioning a second glass layer on said first capacitive dielectric layer and substantially over said second conductor, said second glass layer having a first surface;

forming a first thru-hole electrical connection to said first conductor;

forming a second thru-hole electrical connection to said second conductor, said first and second conductors and said capacitive dielectric layer forming a capacitor when said capacitive substrate is in operation; and

heat treating, including laser annealing, said capacitive dielectric layer on said first surface of said first glass layer and substantially over said first conductor at a first a pre-established temperature.

10. The method of claim 9 further including heat treating said second glass layer on said first capacitive dielectric layer and substantially over said second conductor at a second pre-established temperature wherein said first pre-established temperature is within the range of from about 400 degrees Celsius to about 800 degrees Celsius and said second pre-established temperature is within the range of from about 400 degrees Celsius to about 1000 degrees Celsius.

Assignments (11)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →