IP Library Granted Patent US 9,526,184
Granted Patent B2
US 9,526,184 · App. 13/537,361 · Granted Dec 20, 2016

Circuit board multi-functional hole system and method

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Quick Facts
Patent No.
US 9,526,184
App. No.
13/537,361
Granted
Dec 20, 2016
Kind
B2
Abstract

A method and system for constructing a printed circuit board with multifunctional holes. A first conductive material is deposited into a hole in a substrate to form a first plating on an inner surface of the hole. At least one outer portion of the hole is modified to have a larger diameter than the original hole and to remove the first conductive material from that outer portion. A seed material is deposited into the modified hole. An etchant is applied to the hole to non-mechanically remove the first conductive material from the unmodified portion of the hole. Another conductive material is deposited to into the modified hole that adheres to the seed material in the modified outer portion via to form a second plating at the outer portion.

Claims (30)

1. A method for selectively plating a via of a multi-layered substrate, the method comprising:

forming a via through a multi-layered substrate, the via having a first diameter and a first inner surface;

depositing a first conductive material into the via to form a plated via including a first plating on the first inner surface;

modifying the plated via to comprise a medial portion, a first outer portion, and a second outer portion, wherein:

the medial portion comprises the first diameter and the first inner surface, and has first conductive material remaining on the first inner surface;

the first outer portion comprises a second diameter and a second inner surface bare of the first conductive material; and

the second outer portion comprises a third diameter and a third inner surface bare of the first conductive material, and wherein the second and third diameters are larger than the first diameter;

depositing a second conductive material, where the second conductive material is a conductive polymer or contains a concentration of carbon or graphite, onto at least the second inner surface and the third inner surface of the modified plated via;

removing the remaining first conductive material from the medial portion by applying an etchant to the modified plated via; and

depositing a third conductive material into the modified plated via to form a second plating on the second conductive material deposited on the second and third inner surfaces of the modified plated via.

2. The method of claim 1 wherein the first conductive material is deposited using electroless copper plating.

3. The method of claim 1 wherein the second conductive material is a conductive polymer that does not adhere to the first conductive material.

4. The method of claim 1 wherein the third conductive material adheres to the second conductive material on the second and third inner surfaces and does not adhere to the first inner surface.

5. The method of claim 1 wherein modifying the via comprises back drilling the via to a predetermined depth from opposite sides to form the first outer portion and the second outer portion.

6. The method of claim 1 wherein removing the first conductive material from the medial portion electrically isolates the second plating on the second surface from the second plating on the third surface.

7. The method of claim 1 wherein applying an etchant comprises microetching the first conductive material from the medial portion.

8. The method of claim 1 wherein:

depositing the second conductive material comprises depositing the second conductive material onto the second inner surface, the third inner surface, and the first conductive material at the medial portion of the modified via; and

removing the second conductive material and the first conductive material from the medial portion by applying the etchant to the modified via; and

wherein the second conductive material is a seed material that comprises graphite.

9. The method of claim 1 wherein the third conductive material is copper plating.

10. A process for selectively plating a hole of a printed circuit board, the process comprising:

forming a hole through a printed circuit board, the hole having a first diameter and a first inner surface;

depositing a first conductive material into the hole to form a plated hole comprising a first plating on the first inner surface;

modifying the plated hole to comprise a first portion and a second portion, wherein:

the first portion comprises the first diameter and the first inner surface, and has first conductive material remaining on the first inner surface; and

the second portion comprises a second diameter and a second inner surface bare of the first plating and wherein the second diameter is larger than the first diameter;

depositing a second conductive material, where the second conductive material is a conductive polymer or contains a concentration of carbon or graphite, onto the second inner surface in the modified plated hole;

removing the first conductive material from the first portion by applying an etchant to the modified plated hole; and

depositing a third conductive material into the modified hole to form a second plating on the second conductive material deposited on the second inner surface of the modified plated hole.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (035858/0890) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
MERGER Recorded May 12, 2023
From: VIASYSTEMS, INC.
To: VIASYSTEMS GROUP, INC.
Reel/Frame 063628/0122 →
MERGER Recorded May 12, 2023
From: VIASYSTEMS GROUP, INC.
To: TTM TECHNOLOGIES, INC.
Reel/Frame 063629/0313 →
PATENT SECURITY AGREEMENT-ABL Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035858/0890 →
PATENT SECURITY AGREEMENT-TERM Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035851/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2012
From: LECESSE, ROY J.
To: VIASYSTEMS, INC.
Reel/Frame 028586/0191 →