IP Library Granted Patent US 8,250,751
Granted Patent B2
US 8,250,751 · App. 12/070,811 · Granted Aug 28, 2012

Method of manufacturing a printed circuit board

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Quick Facts
Patent No.
US 8,250,751
App. No.
12/070,811
Granted
Aug 28, 2012
Kind
B2
Abstract

Printed circuit boards have circuit layers with one or more copper filled through-holes and methods of manufacturing the same. An aspect of an embodiment of the present invention enhances thermal characteristics of filled through-holes of printed circuit boards to provide extra reliability to the printed circuit boards. In one embodiment, a printed circuit broad has a plurality of through-holes to connect copper patterns on different layers of the printed circuits broad. Here, at least one of the through-holes is copper plated closed at both ends with at least 70% volume of the through-hole plated with copper to, e.g., enhance thermal characteristics of the through-hole, thereby providing extra reliability to the printed circuit board. In one embodiment, the printed circuit board includes a surface conductor (or cap) that is directly plated over the copper filled barrel plated through-hole.

Claims (34)

1. A method of manufacturing a printed circuit board having a plurality of circuit layers with at least one through-hole to connect copper patterns on different layers of the printed circuit board, the method comprising:

drilling at least one through-hole into a laminated structure with a first solid copper layer and a second solid copper layer respectively as both outermost layers of the laminated structure;

metalizing the drilled circuit layers with the at least one through-hole;

applying a resist on both outermost layers of the circuit layers;

patterning the resist on both outermost layers of the circuit layers to expose the at least one through-hole to an electrolytic plating solution;

electrolytic copper plating the at least one through-hole with the electrolytic plating solution to fill close the at least one through-hole with copper;

removing the resist;

planarizing excess copper plated on both outermost layers of the circuit layers to expose both outermost layers of the circuit layers;

cleaning the planarized circuit layers with the copper filled through holes;

applying a second resist on at least one outermost layer of the outermost layers with the copper filled through-hole;

patterning the second resist on the at least one outermost layer to image a conductive cap on the copper filled through-hole; and

plating copper directly on the copper filled through-hole to form the conductive cap.

2. A method of manufacturing a printed circuit board having a plurality of circuit layers with at least one through-hole to connect copper patterns on different layers of the printed circuit board, the method comprising:

laminating the plurality of circuit layers with each other to form the circuit board with a first solid copper layer and a second solid copper layer respectively as both outermost layers of the circuit board;

drilling at least one through-hole into the laminated circuit layers;

metalizing the drilled circuit layers with the at least one through-hole;

applying a resist on both outermost layers of the circuit layers;

patterning the resist on both outermost layers of the circuit layers to expose the at least one through-hole to an electrolytic plating solution;

electrolytic copper plating the at least one through-hole with the electrolytic plating solution to fill close the at least one through-hole with copper;

removing the resist;

planarizing excess copper plated on both outermost layers of the circuit layers to expose both outermost layers of the circuit layers;

cleaning the planarized circuit layers with the copper filled through holes;

applying a second resist on at least one outermost layer of the circuit layers with the copper filled through-hole;

patterning the second resist on the at least one outermost layer of the circuit layers to image a conductive cap on the copper filled through-hole; and

plating copper directly on the copper filled through-hole to form the conductive cap.

3. The method of claim 2 , wherein the at least one through-hole is formed by mechanical drilling.

4. The method claim 2 ,

wherein the applying the second resist comprises applying the second resist on both outermost layers of the circuit layers with the copper filled through-hole; and

the method further comprising: etching the at least one outermost layer of the circuit layers to form the circuit board.

5. The method of claim 2 , wherein the conductor cap is formed to directly plate on the copper filled through-hole at each end of the copper filled through-hole.

6. The method of claim 2 , wherein the copper plating the at least one through-hole with the electrolytic plating solution to plate close the at least one through-hole comprises barrel plating the at least one through-hole with the electrolytic plating solution to plate close the at least one through-hole.

7. The method of claim 2 , wherein the copper plating the at least one through-hole with the electrolytic plating solution to plate close the at least one through-hole comprises plating the at least one through-hole with at least 70% volume of the at least one though-hole with copper.

8. The method of claim 2 , wherein the copper plating the at least one through-hole with the electrolytic plating solution to plate close the at least one through-hole comprises plating the at least one through-hole with enough electrolytic plated copper to plate close both ends of the at least one through-hole.

9. The method of claim 2 , wherein the copper plating the at least one through-hole with the electrolytic plating solution to plate close the at least one through-hole comprises enhancing a thermal characteristic of the at least one through-hole.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (035858/0890) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
CHANGE OF NAME Recorded Sep 9, 2019
From: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 050314/0305 →
PATENT SECURITY AGREEMENT-TERM Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035851/0928 →
PATENT SECURITY AGREEMENT-ABL Recorded Jun 8, 2015
From: TTM TECHNOLOGIES, INC.; VIASYSTEMS, INC.; VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 035858/0890 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2014
From: VIASYSTEMS NORTH AMERICA OPERATIONS, INC.
To: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
Reel/Frame 031937/0500 →
CHANGE OF NAME Recorded Dec 31, 2013
From: DDI GLOBAL CORP.
To: VIASYSTEMS NORTH AMERICA OPERATIONS, INC.
Reel/Frame 031863/0129 →
CHANGE OF NAME Recorded Jul 19, 2012
From: DYNAMIC DETAILS, INCORPORATED
To: DDI GLOBAL CORP.
Reel/Frame 028603/0854 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2012
From: JPMORGAN CHASE BANK, N.A.,
To: DDI GLOBAL CORP.
Reel/Frame 028425/0777 →
SECURITY AGREEMENT Recorded Nov 30, 2010
From: DDI GLOBAL CORP.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 025321/0451 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2008
From: SIDHU, RAJWANT, MR.; WALKER, PAUL, MR.
To: DYNAMIC DETAILS, INC.
Reel/Frame 021227/0892 →