IP Library › Assignment 025321/0451
Patent Assignment
Reel/Frame 025321/0451

Security Agreement

Recorded: 2010-11-30 Received: 2010-11-30 Pages: 9
Assignor
DDI GLOBAL CORP.
Executed: 2010-09-23
Assignee
JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
3 PARK PLAZA, 9TH FLOOR, IRVINE, CA, 92614, UNITED STATES
Covered Properties (10)
Systems and Methods for Reducing Overhang on Electroplated Surfaces of Printed Circuit Board
Application: 61/355,914 →
Methods of Manufacturing Printed Circuit Boards Using Internal Stacked Micro Vias to Couple Subassemblies
Application: 61/351,253 →
Methods of Manufacturing Printed Circuit Boards Using Parallel Processes to Interconnect with Subassemblies
Methods of Manufacturing Printed Circuit Boards
Application: 12/772,086 →
Additional Functionality Single Lammination Stacked via with Plated Through Holes for Multilayer Printed Circuit Boards
Manufacturing Methods of Multilayer Printed Circuit Board Having Stacked Via
Application: 12/539,172 →
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Application: 12/381,925 →
Method of Manufacturing a Multilayer Printed Wiring Board with Copper Wrap Plated Hole
Application: 12/157,021 →
Method of Manufacturing a Printed Circuit Board
Application: 12/070,811 →
Methods of Manufacturing Printed Circuit Boards with Stacked Micro Vias
Application: 11/706,473 →