IP Library Granted Patent US 7,856,706
Granted Patent B2
US 7,856,706 · App. 12/381,925 · Granted Dec 28, 2010

Methods of manufacturing printed circuit boards with stacked micro vias

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Quick Facts
Patent No.
US 7,856,706
App. No.
12/381,925
Granted
Dec 28, 2010
Kind
B2
Abstract

A method of manufacturing at least a portion of a printed circuit board. The method includes: applying a lamination adhesive on a first plural-layer substrate that includes a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate; applying a protective film on the lamination adhesive; forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate; filling at least one conductive paste into the at least one via formed in the lamination adhesive; removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and attaching the first plural-layer substrate with a second plural-layer substrate that includes a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.

Claims (17)

1. A method of manufacturing at least a portion of a printed circuit board, the method comprising:

applying a lamination adhesive on a first plural-layer substrate comprising a plurality of circuit layers with at least one first metal pad on a first side of the first plural-layer substrate;

applying a protective film on the lamination adhesive;

forming at least one via into the lamination adhesive to expose the at least one metal pad on the first side of the first plural-layer substrate;

filling at least one conductive paste into the at least one via formed in the lamination adhesive;

removing the protective film to expose the lamination adhesive on the first plural-layer substrate; and

attaching the first plural-layer substrate with a second plural-layer substrate comprising a plurality of circuit layers with at least one second metal pad on a second side of the second plural-layer substrate.

2. The method of claim 1 , wherein the attaching of the first plural-layer substrate with the second plural-layer substrate comprises:

aligning the first plural-layer substrate with the second plural-layer substrate such that the lamination adhesive is between the first side of the first plural-layer substrate and the second side of the second plural-layer substrate and that the at least one second metal pad on the second side contacts the at least one conductive paste filled into the at least one via; and

curing the lamination adhesive substrates between the first side of the first plural-layer substrate and the second side of the second plural-layer substrate to laminate the first plural-layer substrate with the second plural-layer substrate.

3. The method of claim 1 , wherein the at least one via is formed by laser drilling.

4. The method of claim 1 , wherein the at least one via is formed by mechanical drilling.

5. The method of claim 1 , further comprising:

imaging at least one photo resist onto the first plural-layer substrate having a metal foil formed on the first side of the first pleural layer substrate;

etching off the metal foil from the first plural-layer substrate with exception of at least one part of the metal foil covered by the at least one photo resist; and

stripping off the at least one photo resist to expose the at least one part of the metal foil to form the at least one first metal pad on the first side of the first plural-layer substrate.

6. The method of claim 1 , wherein the at least one via has a diameter between about 0.004″ and about 0.010″.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (035858/0890) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TTM TECHNOLOGIES, INC. (FORMERLY KNOWN AS VIASYSTEMS GROUP, INC. AND VIASYSTEMS, INC.); TTM TECHNOLOGIES NORTH AMERICA, LLC (FORMERLY KNOWN AS VIASYSTEMS TECHNOLOGIES CORP., L.L.C.)
Reel/Frame 075681/0922 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
CHANGE OF NAME Recorded Sep 9, 2019
From: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 050314/0305 →