IP Library Granted Patent US 11,711,885
Granted Patent B2
US 11,711,885 · App. 17/162,773 · Granted Jul 25, 2023

Method of manufacturing printed circuit board assemblies with engineered thermal paths

Inventors: Rick Bauer (East Syracuse, NY); Jerrad Martinson (East Syracuse, NY); Shane Hoffstatter (East Syracuse, NY); Doyle Laudal (East Syracuse, NY); Mike Lugert (East Syracuse, NY); Mike Len (East Syracuse, NY)
Assignee: TTM Technologies, Inc.
H05K1/0203H05K3/4076H05K2203/1572
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Quick Facts
Patent No.
US 11,711,885
App. No.
17/162,773
Granted
Jul 25, 2023
Kind
B2
Abstract

A printed circuit board (PCB) having an engineered thermal path and a method of manufacturing are disclosed herein. In one aspect, the PCB includes complementary cavities formed on opposite sides of the PCB. The complementary cavities are in a thermal communication and/or an electrical communication to form the engineered thermal path and each cavity is filled with a thermally conductive material to provide a thermal pathway for circuits and components of the PCB. The method of manufacturing may further include drilling and/or milling each cavity, panel plating the cavities and filling the cavities with a suitable filling material.

Claims (24)

1. A method for forming a printed circuit board having an engineered thermal path, the method comprising:

forming a first cavity in a top surface of the printed circuit board by drilling, milling, or a combination thereof into the top surface of the printed circuit board to a first depth;

plating the first cavity and the top surface of the printed circuit board to form a first plated metal layer;

filling the first cavity with a first thermal conductive material;

forming a second cavity in a bottom surface of the printed circuit board by drilling, milling, or a combination thereof into the bottom surface of the printed circuit board to a second depth;

plating the second cavity and the bottom surface of the printed circuit board to form a second plated metal layer; and

filling the second cavity with a second thermal conductive material, wherein the filled first cavity is in thermal communication, electrical communication, or both thermal and electrical communication with the filled second cavity to form a filled cavity structure as an engineered thermal path, an electrical path, or both, wherein the first cavity is enclosed by first side surfaces coupled to a first bottom formed of a portion of the first plated metal layer, wherein the second cavity is enclosed by second side surfaces coupled to a second bottom formed of a portion of the second plated metal layer.

2. The method of claim 1 , wherein the second cavity is formed to have different dimensions or a greater cross-sectional area than the first cavity.

3. The method of claim 1 , wherein the second cavity is formed to have same dimensions as the first cavity.

4. The method of claim 1 , wherein the second cavity is formed to be adjoining with the first cavity via the first and second plated metal layers.

5. The method of claim 1 , further comprising planarizing at least one of the top surface and the bottom surface.

6. The method of claim 1 , wherein the first thermal conductive material and the second thermal conductive material are selected from a group consisting of copper, tin, gold, silver, nickel, aluminum, conductive polymers, conductive epoxies, non-conductive polymers, and combinations thereof.

7. The method of claim 1 , wherein the first thermal conductive material and the second thermal conductive material have a same composition or different compositions.

8. A method for forming a printed circuit board having an engineered thermal path, the method comprising:

forming a first cavity in a top surface of the printed circuit board (PCB) by drilling, milling, or a combination thereof into the top surface of the printed circuit board to a first depth;

plating the PCB and the first cavity to form a first plated metal layer;

forming a second cavity in a bottom surface of the printed circuit board by drilling, milling, or a combination thereof into the bottom surface of the printed circuit board to a second depth;

plating the PCB and the second cavity to form a second plated metal layer;

applying a photoresist mask to the PCB to expose the first cavity and the second cavity; and

simultaneously plating to fill the first cavity and the second cavity with a thermal conductive material, wherein the first cavity is in thermal communication, electrical communication, or both thermal and electrical communication with the second cavity to form a filled cavity structure as an engineered thermal path, an electrical path, or both, wherein the second cavity is formed to be directly adjoining with the first cavity via the first and second plated metal layers, wherein the first cavity is enclosed by first side surfaces coupled to a first bottom formed of a portion of the first plated metal layer, wherein the second cavity is enclosed by second side surfaces coupled to a second bottom formed of a portion of the second plated metal layer.

9. The method of claim 8 , wherein the second cavity is formed to have different dimensions or a greater cross-sectional area than the first cavity.

10. The method of claim 8 , wherein the second cavity is formed to have same dimensions as the first cavity.

11. The method of claim 1 , wherein one of the first or second plated metal layer has a thickness ranging from 2 mils to 6 mils.

12. The method of claim 8 , wherein one of the first or second plated metal layer has a thickness ranging from 2 mils to 6 mils.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2021
From: BAUER, RICK; MARTINSON, JERRAD; HOFFSTATTER, SHANE; LAUDAL, DOYLE; LUGERT, MIKE; LEN, MIKE
To: ANAREN, INC.
Reel/Frame 057783/0550 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: ANAREN, INC.
To: TTM TECHNOLOGIES INC.
Reel/Frame 056635/0640 →