IP Library Granted Patent US 8,144,480
Granted Patent B2
US 8,144,480 · App. 12/720,849 · Granted Mar 27, 2012

Multi-layer embedded capacitance and resistance substrate core

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Quick Facts
Patent No.
US 8,144,480
App. No.
12/720,849
Granted
Mar 27, 2012
Kind
B2
Abstract

A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.

Claims (29)

1. A method of making a multi-layer embedded capacitance and resistance substrate core, the steps comprising:

a) providing a Laser drillable dielectric having an upper surface and a lower surface;

b) disposing a first resistance layer on the upper surface of said Laser drillable dielectric;

c) disposing a first electrically conductive layer on said first resistance layer;

d) laminating said laser drillable dielectric, said first resistance layer and said first electrically conductive layer to form a first resistance structure;

e) applying and developing a first resist to said first electrically conductive layer;

f) selectively etching said first electrically conductive layer;

g) stripping said first resist from said first electrically conductive layer;

h) disposing a first copper-coated capacitance layer on said first electrically conductive layer;

i) laminating said first copper-coated capacitance layer and said first resistance structure;

j) applying and developing a second resist on said first resistance structure;

k) stripping said second resist; and

l) selectively etching said first copper-coated capacitance layer.

2. The method of making a multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , wherein said electrically conductive layer comprises copper foil.

3. The method of making a multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , the steps further comprising laser-forming thru-holes in said substrate.

4. The method of making a multi-layer embedded capacitance and resistance substrate core in accordance with claim 1 , the steps further comprising:

m) disposing a second resistance layer on the lower surface of said laser drillable dielectric;

n) disposing a second electrically conductive layer on said second resistance layer;

o) laminating said laser drillable dielectric, said second resistance layer and said second electrically conductive layer to form a second resistance structure;

p) applying and developing a third resist to said second electrically conductive layer;

q) selectively etching said second electrically conductive layer;

r) stripping said third resist from said second electrically conductive layer;

s) disposing a second copper-coated capacitance layer on said second electrically conductive layer;

t) laminating said second copper-coated capacitance layer and said second resistance structure;

u) applying and developing a fourth resist on said second resistance structure;

v) stripping said fourth resist; and

w) selectively etching said second copper-coated capacitance layer.

5. The method of making a multi-layer embedded capacitance and resistance substrate core in accordance with claim 4 , wherein said second electrically conductive layer comprises copper foil.

6. The method of making a multi-layer embedded capacitance and resistance substrate core in accordance with claim 4 , the steps further comprising laser-forming thru-holes in said substrate.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →