Method of making a multi-chip electronic package having laminate carrier
View Patent ↗A method of making a multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.
1. A method of making a multi-chip electronic package comprising:
providing an organic, laminate chip carrier having first and second surfaces and including a plurality of electrically conductive planes spacedly positioned therein and separated by respective layers of dielectric material, at least one of said layers of dielectric material being comprised of polytetrafluoroethylene (PTFE);
providing a plurality of electrical contacts on said first surface of said organic, laminate chip carrier;
providing a plurality of electrical conductors on said second surface of said organic, laminate chip carrier, selected ones of said electrical contacts being electrically coupled to selected ones of said electrical conductors;
positioning an application specific integrated circuit (ASIC) semiconductor chip on said first surface of said organic, laminate chip carrier and electrically coupling said ASIC semiconductor chip to said selected ones of said electrical contacts using a first plurality of solder balls;
positioning a memory semiconductor chip on said ASIC semiconductor chip using an adhesive such that said ASIC and memory semiconductor chips form a stacked orientation, said positioning of said memory semiconductor chip including positioning of a second plurality of solder balls between said memory semiconductor chip and said ASIC semiconductor chip to provide a thermal path between said ASIC semiconductor chip and said memory semiconductor chip;
electrically coupling said memory semiconductor chip to others of said selected ones of said electrical contacts using a wirebond operation while said memory semiconductor chip is positioned on said ASIC semiconductor chip and said second plurality of solder balls are positioned between said ASIC semiconductor chip and said memory semiconductor chip; and
positioning a metal heat-sinking member substantially over said ASIC semiconductor chip and said memory semiconductor chip.
2. The method of claim 1 wherein said positioning of said memory semiconductor chip on said ASIC semiconductor chip using said second plurality of solder balls provides a desired spacing between said memory semiconductor chip and said ASIC semiconductor chip.
3. The method of claim 1 further including positioning a stiffener member on said first surface of said organic, laminate chip carrier about said ASIC semiconductor chip and said memory semiconductor chip, and thereafter positioning said metal heat sinking member on said stiffener member.
4. The method of claim 1 wherein said providing of said organic, laminate chip carrier includes providing said organic, laminate chip carrier with a first multilayered portion including at least one dielectric layer and at least one conductive plane wherein said conductive plane includes signal lines for having signals pass therealong at a first frequency and with a second multilayered portion bonded to said first multilayered portion and for having said ASIC and memory semiconductor chips coupled thereto, said second multilayered portion including at least one dielectric layer and at least one conductive signal plane wherein said conductive signal plane of said second multilayered portion includes signal lines capable of having signals pass therealong at a higher frequency than said first frequency to thereby provide a high speed connection between said first and second semiconductor chips.
5. The method of claim 1 further including providing a thermally conductive member within said organic, laminate chip carrier having a selected thickness and coefficient of thermal expansion to substantially prevent failure of said electrical couplings provided by said first plurality of solder balls electrically coupling said ASIC semiconductor chip to said selected ones of said electrical contacts.