IP Library Granted Patent US 7,712,210
Granted Patent B2
US 7,712,210 · App. 11/808,140 · Granted May 11, 2010

Method of providing a printed circuit board with an edge connection portion

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Quick Facts
Patent No.
US 7,712,210
App. No.
11/808,140
Granted
May 11, 2010
Kind
B2
Abstract

A method of making a printed circuit board in which at least two circuitized substrates are aligned and bonded together (e.g., using lamination). A gasket is provided on one of these and a facing circuitized portion on the other. The gasket forms an effective seal about the circuitized portion to prevent heated dielectric material from contacting the circuitry. After bonding, parts of the bonded structure, including the gasket, are removed to leave a projecting edge portion having circuitry thereon. This edge portion is then adapted for being positioned within an edge connector.

Claims (21)

1. A method of making a printed circuit board, said method comprising:

providing a first circuitized substrate including a first part having a first surface including a circuitized portion thereon;

providing a second circuitized substrate including a first part having a first surface including a sealing gasket thereon;

aligning said first and second circuitized substrates relative to one another such that said circuitized portion on said first surface of said first part of said first circuitized substrate aligns with said sealing gasket on said first surface of said first part of said second circuitized substrate;

bonding said first and second circuitized substrates together such that said gasket on said first surface of said first part of said second circuitized substrate forms a seal about said circuitized portion on said first surface of said first part of said first circuitized substrate for preventing wet chemistry interaction; and

thereafter removing said first part of said second circuitized substrate, including said sealing gasket, to leave a remaining part of said second circuitized substrate, said first part of said first circuitized substrate having said first surface having said circuitized portion thereon and said remaining part of said second circuitized substrate forming a printed circuit board.

2. The method of claim 1 further including positioning a layer of dielectric material substantially between said first and second circuitized substrates prior to said bonding of said first and second circuitized substrates together and thereafter bonding said first and second circuitized substrates.

3. The method of claim 2 further including providing an opening within said layer of dielectric layer and aligning said opening relative to said circuitized portion on said first surface of said first part of said first circuitized substrate.

4. The method of claim 3 further including heating said first and second circuitized substrates during said bonding sufficiently to cause said layer of dielectric material to flow, said sealing gasket preventing said dielectric material of said layer of dielectric material from contacting said circuitized portion on said first surface of said first part of said first circuitized substrate.

5. The method of claim 4 wherein said first and second circuitized substrates are heated to a temperature within the range of from about 150 degrees Celsius to about 250 degrees Celsius for a time period of from about 60 minutes to about 120 minutes.

6. The method of claim 3 further including applying pressure onto said first and second circuitized substrates during said bonding of said first and second circuitized substrates.

7. The method of claim 6 wherein said pressure is within the range of from about 300 PSI to about 700 PSI.

8. The method of claim 1 wherein said bonding of said first and second circuitized substrates is accomplished utilizing a lamination process.

9. The method of claim 1 wherein said removing of said first part of said second circuitized substrate, including said sealing gasket, is accomplished using a routing procedure.

10. The method of claim 9 further including removing outer portions of said first and second circuitized substrates after said bonding of said first and second circuitized substrates and prior to said removing of said first part of said second circuitized substrate, including said sealing gasket.

11. The method of claim 10 wherein said removing if said outer portions of said first and second circuitized substrates after said bonding of said first and second circuitized substrates and prior to said removing of said first part of said second circuitized substrate, including said sealing gasket, is accomplished using a routing procedure.

12. The method of claim 1 further including providing at least one opening within said first part of said first circuitized substrate having said circuitized portion thereon relative to said circuitized portion, said at least one opening having access to said circuitized portion.

13. The method of claim 12 wherein said at least one opening is adapted for providing escape of gases relative to said circuitized portion which arise during said bonding of said first and second circuitized substrates.

14. The method of claim 1 further including providing at least one opening within said first part of said second circuitized substrate having said sealing gasket thereon relative to said sealing gasket, said at least one opening having access to said circuitized portion.

15. The method of claim 14 wherein said at least one opening is adapted for providing escape of gases relative to said circuitized portion which may arise during said bonding of said first and second circuitized substrates.

16. The method of claim 1 further including positioning an edge connector on said first part of said first circuitized substrate having said first surface having said circuitized portion thereon to form an electrical assembly including said printed circuit board and said edge connector.

Assignments (13)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (063804/0702) Recorded Jun 2, 2026
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 075679/0852 →
PATENT SECURITY AGREEMENT (ABL) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0702 →
PATENT SECURITY AGREEMENT (TERM LOAN) Recorded May 30, 2023
From: TELEPHONICS CORPORATION; TTM TECHNOLOGIES, INC.; TTM TECHNOLOGIES NORTH AMERICA, LLC
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 063804/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2019
From: I3 ELECTRONICS, INC.
To: TTM TECHNOLOGIES NORTH AMERICA, LLC
Reel/Frame 049758/0265 →
SECURITY INTEREST Recorded Nov 14, 2016
From: I3 ELECTRONICS, INC.
To: M&T BANK
Reel/Frame 040608/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: I3 ELECTRONICS, INC.
Reel/Frame 035442/0569 →
RELEASE OF SECURITY INTEREST Recorded Feb 26, 2015
From: MAINES, WILLIAM; MAINES, DAVID
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 035098/0968 →
SECURITY AGREEMENT Recorded Jun 12, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: MAINES, WILLIAM; MAINES, DAVID
Reel/Frame 030599/0918 →
SECURITY AGREEMENT Recorded May 6, 2013
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.; INTEGRIAN HOLDINGS, LLC
To: M&T BANK
Reel/Frame 030359/0057 →
ASSIGNMENT OF SECURITY AGREEMENT Recorded Mar 6, 2013
From: PNC BANK, NATIONAL ASSOCIATION
To: INTEGRIAN HOLDINGS, LLC
Reel/Frame 029938/0823 →
SECURITY AGREEMENT Recorded May 14, 2012
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.; EI TRANSPORTATION COMPANY LLC; ENDICOTT MEDTECH, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028230/0798 →
RELEASE BY SECURED PARTY Recorded May 14, 2012
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
Reel/Frame 028230/0611 →
SECURITY AGREEMENT Recorded Dec 3, 2008
From: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0908 →