Multilayered circuitized substrate with p-aramid dielectric layers and method of making same
View Patent ↗A multilayered circuitized substrate including a plurality of dielectric layers each comprised of a p-aramid paper impregnated with a halogen-free, low moisture absorptivity resin including an inorganic filler but not including continuous or semi-continuous fiberglass fibers as part thereof, and a first circuitized layer positioned on a first of the dielectric layers. A method of making this substrate is also provided.
1. A multilayered circuitized substrate comprising:
a core substrate having a thickness between 20 and 200 microns including a first dielectric layer being no greater than 0.1524 mm, having a p-aramid paper impregnated with a composition including halogen-free, low moisture absorptivity resin including an inorganic particulate filler and not including continuous or semi-continuous fiberglass fibers as part thereof and a first circuitized layer directly positioned on said first thin dielectric layer; and
a second dielectric layer being no greater than 0.1524 mm, bonded to said thin core substrate to form a multilayered circuitized substrate, said second thin dielectric layer being of a composition similar to said composition of said first thin dielectric layer of said thin core substrate, said second dielectric layer not including continuous or semi-continuous fiberglass fibers.
2. The multilayered circuitized substrate of claim 1 wherein said thin core substrate has a thickness of about 270 microns or less.
3. The multilayered circuitized substrate of claim 1 wherein said low moisture absorptivity resin of said first and second thin dielectric layers comprises a high Tg polymer.
4. The multilayered circuitized substrate of claim 3 wherein said low moisture absorptivity resin of said first and second thin dielectric layers has less than about 0.5 percent moisture absorption when immersed in water for a period of about 24 hours at a temperature of about 22° C.
5. The multilayered circuitized substrate of claim 1 wherein said first and second thin dielectric layers each have a coefficient of thermal expansion in the x and y direction less than about 23 parts per million/degree C.
6. The multilayered circuitized substrate of claim 1 wherein said first and second thin dielectric layers each include a plurality of thru-holes therein, said thru-holes being in a pattern having a density of from about 5,000 thru-holes per square inch to about 10,000 thru-holes per square inch.
7. The multilayered circuitized substrate of claim 1 wherein said first circuitized layer is comprised of copper.
8. The multilayered circuitized substrate of claim 1 wherein said thin core substrate further includes a second circuitized layer positioned on said first thin dielectric layer on a side opposite said first circuitized layer.
9. The invention of claim 8 wherein said multilayered circuitized substrate further includes third and fourth thin dielectric layers, said third and fourth thin dielectric layers each being of a composition similar to said composition of said first thin dielectric layer of said thin core substrate.
10. The invention of claim 9 wherein said multilayered circuitized substrate comprises a chip carrier.
11. The multilayered circuitized substrate of claim 1 further including at least one electrical component positioned on and electrically coupled to said multilayered circuitized substrate, said multilayered circuitized substrate and said component forming an electrical assembly.
12. The multilayered circuitized substrate of claim 11 wherein said electrical component comprises a semiconductor chip.
13. The multilayered circuitized substrate of claim 11 wherein said electrical component comprises a chip carrier.